EDA Skillpack

Find relevant EDA skills across Adom bridges, web tools and specialized skillpacks. Use when choosing an EDA workflow or applying shared guidance across tools, and before running any KiCad command in a container (kicad-cli, DRC, ERC, gerbers, STEP, pcbnew): KiCad is never installed locally, it runs on service-kicad or the user's desktop.

Use when choosing, placing, wiring or reviewing single-wire addressable RGB LEDs (WS2812B, WS2812B-2020, -V6, -V7, WS2812C, WS2812E, NeoPixel, SK6812-style, Dialight 587-1024-147F) in a schematic or PCB, including 3.3 V data drive, chain power budgets, substituting one 2020 part for another, and pin-1 orientation. Trigger words: WS2812, NeoPixel, addressable LED, RGB LED chain, LED strip, pixel LED, 2020 LED, DIN DOUT chain, level shift WS2812, LED power budget.

Review PCB placement, solder-mask, thermal-pad and via decisions against pick-and-place, solder jetting or paste deposition, reflow and inspection requirements before preparing assembly outputs.

Compare original and redesigned PCB assemblies in the native EDA 3D viewer. Use when asked to show my board in 3D, compare component placement, inspect stacked modules, explain symmetry or check assembly access.

Calculate PCB component placement from nets, footprints, power paths and mechanical interfaces. Use when asked to move all components off the board, place my PCB, optimize placement, preserve connector grids, or compare layout symmetry.

Route PCBs for copper ablation by retaining copper on every layer, including intentionally floating islands when requested. Measure native filled copper coverage, preserve electrical isolation, and record reproducible CAD demonstrations.

Make a narrated evidence-based video of PCB placement, routing, validation and native 3D comparison. Use when asked to show the team what the AI did, summarize my PCB redesign, record a before and after, or make an engineering meeting video.

Route or review a PCB with electrical constraints, power and ground pours, clean signal geometry, and copper-retention goals for subtractive or copper-ablation fabrication. Use before claiming an AI-routed board is electrically ready or recording a production-oriented routing demo.

Carry an independently generated PCB placement through routing, power and thermal copper planning, ablation-aware retention and native validation. Use for complete AI board layouts and fair engine comparisons; preserve design provenance and distinguish a worked-example planner from a reusable router.

Escape and fan out a 0.4 mm pitch QFN or similar fine-pitch part with a planner - stub widths, reserved escape corridors on the top and inner layers, dog-bone via classes, nested side ordering, power-pin escapes, and rip-up/re-route for boxed-in pins. Use when a planner keeps failing single pins at a dense IC.

Re-route an existing hand-routed board independently with your own planner and compare it fairly against the original (or another AI's run) with native baselines, a proven strip, diagnostic rule copies, native DRC on the actual replay, and a side-by-side net-highlight video. Use when asked to "route this board from scratch and compare".

Use when placing or routing shunts and current-sense amplifiers, or reviewing pours near Kelvin sense traces, including a sense return named GND and sense vias crossing copper planes.

Use when placing or reviewing an ESC, H-bridge, inverter or motor-driver PCB, especially MOSFET power loops, gate returns, bypass capacitors, thermal copper and multilayer vias.

Review multilayer PCB copper connectivity, matched-net X-ray comparisons and modeled DC current paths. Use for power-path bottlenecks, supply-plane stitching, retained floating copper and current-density overlays in any EDA tool.

Make generated copper count as connected in Fusion Electronics / EAGLE - endpoint rules for wires, pads, vias and package copper, same-signal via clearance, drill classes, live-command pitfalls - so the native ratsnest reports zero airwires. Use before validating or replaying planner output in Fusion.

Coordinate an independent PCB placement, trace routing, native 3D review and narrated comparison. Use when asked to place and route my board, start from an empty board, compare AI and human placement, or show the whole PCB design process.

Plan power and ground pours from a placement, connect them across layers with stitching and island vias, run a bounded expansion pass, and measure connected copper honestly (unions, drill voids, islands excluded, native layer images) with reassigned ground reported. Use after routing and before thermal claims.

Turn PCB routing rules into measured gates that fail the build - 0/45/90 geometry, no extra bends, no via inside a trace, cap-first decoupling, measured decoupling loops, power-stage loop distances, an unbroken plane under the hot loop, and power paths that must not neck or wander (a switching trace thinner than the pin it leaves). Use after routing and before calling a board done, when reviewing someone else's layout, or when a reviewer points at a trace and you want the check that would have caught it.

Review PCB thermal plots and narrow copper connections, then reroute suitable obstructing traces across layers to improve heat spreading while preserving electrical and assembly constraints.

Route a PCB visibly with clean trace geometry, electrical priorities, expanded net-connected copper pours and thermal bottleneck review. Use for live AI routing in Fusion, KiCad, Altium or another supported EDA tool.