skill
EDA Skillpack
Public Made by Adomby adom
All skills for all EDA capabilities across the Adom ecosystem.
main
John Lauer
Add Fable 5.1 BQ25792 independent re-route example (side-by-side video, evidence, four shared skills)
9458d54
28d ago
name: eda-fine-pitch-fanout description: Escape and fan out a 0.4 mm pitch QFN or similar fine-pitch part with a planner - stub widths, reserved escape corridors on the top and inner layers, dog-bone via classes, nested side ordering, power-pin escapes, and rip-up/re-route for boxed-in pins. Use when a planner keeps failing single pins at a dense IC.
Parent skill: eda-engineering
Fan-out is a discipline, not a search parameter
On the BQ25792 example (33 pads, 0.4 mm pitch, 0.2 mm pads, caps 1.2-1.5 mm in front of two sides) a plain A* failed 3-6 pins per run for twelve iterations; the following rules took it to 50/50 nets.
- Stub every fine-pitch pin straight out by its pad width for 0.7 mm (0.15 mm for signals, the full 0.2 mm for power pins) before any net is routed; the stub is committed copper of that net.
- Reserve an escape corridor in front of every unrouted pin (about 1.6 mm on the top layer) that other nets may not cross; release it when the pin is routed. Without it, the first net to route drops a via or a turn in front of its neighbours and boxes them in.
- Signal pins also reserve a via-landing corridor on the inner/bottom layers (0.5 mm wide, about 2.5 mm) so wide power routes on the bottom layer do not occupy every dog-bone spot. Power pins do not need it; a wide net escapes straight or via a via placed beyond the neighbours' stubs.
- Two adjacent pins cannot both take in-line dog-bones with 0.6 mm vias and 0.2 mm stubs at 0.4 mm pitch. Use a signal via class (0.4 mm outer, 0.2 mm drill, inside the inherited minimum-drill rule) with 0.15 mm stubs; stagger distances for neighbours; the via must not intrude the neighbour's lane by more than its clearance.
- Order per side: pins leaving the row in the direction opposite to their neighbours first (they take the vias), then nested turns from the pin nearest the turn direction outward. A pin whose destination is on the far side of its own row needs a via, not a detour around the corner.
- Keep wide power escapes narrow until the neighbouring signal pins can turn (the example needed 2.8 mm for the two BAT pins next to the /INT pin), and document the current density of that neck.
- When a pin is still boxed in, rip up the nearest blocking neighbours, route the boxed pin first, re-route the neighbours; place any remaining dog-bone with an exact-geometry legality test rather than the raster.
- Search hygiene that mattered: key the A* state on (layer, cell) with a bend penalty (a direction-keyed state exhausts node caps on long detours); use a strict inequality in clearance dilation so a via at exactly the required distance is legal; keep an exact raster for connectivity separate from the padded raster for clearance, and never dilate the exact one.
---
name: eda-fine-pitch-fanout
description: Escape and fan out a 0.4 mm pitch QFN or similar fine-pitch part with a planner - stub widths, reserved escape corridors on the top and inner layers, dog-bone via classes, nested side ordering, power-pin escapes, and rip-up/re-route for boxed-in pins. Use when a planner keeps failing single pins at a dense IC.
---
Parent skill: eda-engineering
# Fan-out is a discipline, not a search parameter
On the BQ25792 example (33 pads, 0.4 mm pitch, 0.2 mm pads, caps 1.2-1.5 mm in front of two sides) a plain A* failed 3-6 pins per run for twelve iterations; the following rules took it to 50/50 nets.
- Stub every fine-pitch pin straight out by its pad width for 0.7 mm (0.15 mm for signals, the full 0.2 mm for power pins) before any net is routed; the stub is committed copper of that net.
- Reserve an escape corridor in front of every unrouted pin (about 1.6 mm on the top layer) that other nets may not cross; release it when the pin is routed. Without it, the first net to route drops a via or a turn in front of its neighbours and boxes them in.
- Signal pins also reserve a via-landing corridor on the inner/bottom layers (0.5 mm wide, about 2.5 mm) so wide power routes on the bottom layer do not occupy every dog-bone spot. Power pins do not need it; a wide net escapes straight or via a via placed beyond the neighbours' stubs.
- Two adjacent pins cannot both take in-line dog-bones with 0.6 mm vias and 0.2 mm stubs at 0.4 mm pitch. Use a signal via class (0.4 mm outer, 0.2 mm drill, inside the inherited minimum-drill rule) with 0.15 mm stubs; stagger distances for neighbours; the via must not intrude the neighbour's lane by more than its clearance.
- Order per side: pins leaving the row in the direction opposite to their neighbours first (they take the vias), then nested turns from the pin nearest the turn direction outward. A pin whose destination is on the far side of its own row needs a via, not a detour around the corner.
- Keep wide power escapes narrow until the neighbouring signal pins can turn (the example needed 2.8 mm for the two BAT pins next to the /INT pin), and document the current density of that neck.
- When a pin is still boxed in, rip up the nearest blocking neighbours, route the boxed pin first, re-route the neighbours; place any remaining dog-bone with an exact-geometry legality test rather than the raster.
- Search hygiene that mattered: key the A* state on (layer, cell) with a bend penalty (a direction-keyed state exhausts node caps on long detours); use a strict inequality in clearance dilation so a via at exactly the required distance is legal; keep an exact raster for connectivity separate from the padded raster for clearance, and never dilate the exact one.