EDA Skillpack

New skill eda-routing-gates (landed from PR #3, by the page owner's go-ahead for skill-only changes): the routing rules as measured gates that fail the build:

• 0/45/90 geometry; extra bends; no via inside a trace;
• cap-first decoupling; measured decoupling loops, where untraced is a failure;
• power-stage input-loop distance and area; output-cap clustering; no other-net copper under the hot loop;
• power paths that must not neck below their pin or wander: the trace, and the filled copper, reported separately.

A stdlib checker reads .kicad_pcb (Fusion and Altium boards via KiCad import). It has 15 fail-on-purpose regressions and is calibrated on john/buck-12v5v-molecule (fails 11 gates, including the SW trace at 0.30 mm from a 0.6 mm pin) and adom/buck-12v-5v-1a-molecule 0.1.1 (passes). eda-visible-routing and eda-electrical-routing now link to it.

eda-addressable-rgb-leds: the WS2812B-2020 V1.3 sheet said no capacitor is needed; current sheets (V6 p.5) ask for 100 nF per LED.

New sub-skill eda-addressable-rgb-leds: Worldsemi 2020 variant table (VDD, VIH, current), 3.3 V data drive, chain power budget and caps, decoupling per part, the Dialight VDD/GND swap trap, and the pin-1 orientation chain.