EDA Skillpack
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d08db97
23d ago
name: eda-motor-driver-layout description: Use when placing or reviewing an ESC, H-bridge, inverter or motor-driver PCB, especially MOSFET power loops, gate returns, bypass capacitors, thermal copper and multilayer vias.
Parent skill: eda-engineering
Motor-driver placement and copper review
Read the relevant sections of TI SLVA959B, Best Practices for Board Layout of Motor Drivers, revision B, October 2021. This is a practical review entrypoint, not a substitute for the selected driver's datasheet.
Decisions from the TI guide
- Separate noisy power circuitry from sensitive circuitry by placement and return-path planning. Preserve useful reference continuity; do not automatically split ground because analog and digital nets coexist. See section 1.
- Give the actual thermal-pad net a continuous spreading path. Inspect narrow exits, relief spokes and via connections, not only pour area. Respect package and assembly requirements. See sections 2–3.
- Place vias so their clearances do not sever return planes. Size interlayer paths for their load; the example via table is not a universal current rating. See section 3.
- Keep gate loops short, with the appropriate source/switch reference nearby. Place driver support capacitors at their corresponding pins. See sections 4–5.
- Put local ceramic bypass capacitors at the switching-current loop and bulk storage near the supply entry. Evaluate the complete supply-and-return loop. See section 5.
- Choose MOSFET orientation from its real pinout and resulting power paths. Review any dedicated drain-sense connection independently of the broad supply pour. See section 6.
- Treat current-sense routing as a separate precision path. See section 7 and Kelvin current-sense.
Execute and report
Use this at three checkpoints: before accepting placement, before occupying power corridors with signals, and after native copper refill. Record each finding as: actual refs/pads, layer, observed geometry, consequence, proposed change, and verification result. Make authorized changes through the selected CAD workflow; do not invent unavailable bridge verbs.
Read end-to-end layout for provenance and reroute iteration, and copper ablation for retention objectives. A motor-driver example's capacitor value, gate width, via dimensions or layer stack is not a default for another board.
Deliver a loop/return map, unresolved layout findings, native DRC/connectivity before and after changes, and the operating/stackup assumptions behind any electrical or thermal claim. Passing DRC alone does not close an unverified power-path finding.
---
name: eda-motor-driver-layout
description: Use when placing or reviewing an ESC, H-bridge, inverter or motor-driver PCB, especially MOSFET power loops, gate returns, bypass capacitors, thermal copper and multilayer vias.
---
Parent skill: eda-engineering
# Motor-driver placement and copper review
Read the relevant sections of [TI SLVA959B, Best Practices for Board Layout of Motor Drivers, revision B, October 2021](https://www.ti.com/lit/an/slva959b/slva959b.pdf). This is a practical review entrypoint, not a substitute for the selected driver's datasheet.
## Decisions from the TI guide
- Separate noisy power circuitry from sensitive circuitry by placement and return-path planning. Preserve useful reference continuity; do not automatically split ground because analog and digital nets coexist. See section 1.
- Give the actual thermal-pad net a continuous spreading path. Inspect narrow exits, relief spokes and via connections, not only pour area. Respect package and assembly requirements. See sections 2–3.
- Place vias so their clearances do not sever return planes. Size interlayer paths for their load; the example via table is not a universal current rating. See section 3.
- Keep gate loops short, with the appropriate source/switch reference nearby. Place driver support capacitors at their corresponding pins. See sections 4–5.
- Put local ceramic bypass capacitors at the switching-current loop and bulk storage near the supply entry. Evaluate the complete supply-and-return loop. See section 5.
- Choose MOSFET orientation from its real pinout and resulting power paths. Review any dedicated drain-sense connection independently of the broad supply pour. See section 6.
- Treat current-sense routing as a separate precision path. See section 7 and [Kelvin current-sense](../eda-kelvin-current-sense/SKILL.md).
## Execute and report
Use this at three checkpoints: before accepting placement, before occupying power corridors with signals, and after native copper refill. Record each finding as: actual refs/pads, layer, observed geometry, consequence, proposed change, and verification result. Make authorized changes through the selected CAD workflow; do not invent unavailable bridge verbs.
Read [end-to-end layout](../eda-end-to-end-layout/SKILL.md) for provenance and reroute iteration, and [copper ablation](../eda-copper-ablation/SKILL.md) for retention objectives. A motor-driver example's capacitor value, gate width, via dimensions or layer stack is not a default for another board.
Deliver a loop/return map, unresolved layout findings, native DRC/connectivity before and after changes, and the operating/stackup assumptions behind any electrical or thermal claim. Passing DRC alone does not close an unverified power-path finding.