EDA Skillpack

@@ -47,3 +47,10 @@ The [Codex Astra + KiCad guide](https://wiki.adom.inc/adom/kicad-bridge/files/do The general lessons are in [eda-multilayer-current-review](skills/eda-multilayer-current-review/SKILL.md), linked from the copper-ablation and pour-measurement skills. They apply to any AI and EDA tool: explicit load terminals, native refilled geometry, conductor connectivity, numerical verification, honest legends and validation of the actual saved revision. These are analysis graphics, not a claim that every bridge has a native X-ray or current-field verb. Device-specific values and unresolved checks remain with the worked example.  Read these skills directly from the source while the EDA Skillpack's installable release awaits its reviewed hero. Adding source guidance does not update already-installed packages or instructions loaded in an existing AI conversation.++## TI-based layout skills for Claude and Codex++- [Motor-driver layout](skills/eda-motor-driver-layout/SKILL.md), based on TI SLVA959B.+- [Kelvin current-sense layout](skills/eda-kelvin-current-sense/SKILL.md), based on TI SSZTAD8.++Both are AI-neutral Markdown, with source links, board-specific decision checks and native-refill verification. Read the same files from Claude or Codex. Their numerical examples are not universal board rules. The install script deploys identical files to both agent skill homes.

@@ -12,6 +12,9 @@ Start with the [skill directory](references/skill-directory.md) to find the rele  The bundled shared skills are: +- [Motor-driver layout](skills/eda-motor-driver-layout/SKILL.md): TI-based placement, switching loops, gate returns and thermal paths.+- [Kelvin current-sense layout](skills/eda-kelvin-current-sense/SKILL.md): protect shunt pickup paths through routing, vias and final pours.+ - [End-to-end independent layout](skills/eda-end-to-end-layout/SKILL.md): preserve placement provenance through routing, copper/thermal review and ablation-aware iteration.  - [Multilayer current review](skills/eda-multilayer-current-review/SKILL.md): native conductor connectivity, matched-net X-ray comparisons, explicit DC load cases and floating-copper accounting.

@@ -1,5 +1,27 @@ #!/bin/sh set -eu-# The wiki package loader installs root and nested SKILL.md files for supported agents.-# No CAD installation, AI selection, personal configuration, or machine recipe is changed.-printf '%s\n' 'EDA engineering skills installed; read eda-engineering in your AI skill catalog.'+eda_package_root=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd)+eda_claude_skills="${CLAUDE_CONFIG_DIR:-$HOME/.claude}/skills"+eda_codex_skills="${CODEX_HOME:-$HOME/.codex}/skills"+# Optional isolated root for install verification, without changing HOME or CODEX_HOME.+if [ -n "${EDA_SKILL_INSTALL_ROOT:-}" ]; then+  eda_claude_skills="$EDA_SKILL_INSTALL_ROOT/claude/skills"+  eda_codex_skills="$EDA_SKILL_INSTALL_ROOT/codex/skills"+fi+for eda_agent_skills in "$eda_claude_skills" "$eda_codex_skills"; do+  mkdir -p "$eda_agent_skills/eda-engineering"+  cp "$eda_package_root/SKILL.md" "$eda_agent_skills/eda-engineering/SKILL.md"+  for eda_resource in references skills docs; do+    if [ -d "$eda_package_root/$eda_resource" ]; then+      mkdir -p "$eda_agent_skills/eda-engineering/$eda_resource"+      cp -R "$eda_package_root/$eda_resource/." "$eda_agent_skills/eda-engineering/$eda_resource/"+    fi+  done+  for eda_skill in "$eda_package_root"/skills/eda-*; do+    [ -f "$eda_skill/SKILL.md" ] || continue+    eda_skill_name=$(basename "$eda_skill")+    mkdir -p "$eda_agent_skills/$eda_skill_name"+    cp -R "$eda_skill/." "$eda_agent_skills/$eda_skill_name/"+  done+  printf 'Installed EDA Skillpack into %s\n' "$eda_agent_skills"+done

@@ -41,3 +41,9 @@ Keep a decision in its maintained home. Broad principles such as copper-pour net - [eda-component-placement](../skills/eda-component-placement/SKILL.md): Calculate PCB component placement from nets, footprints, power paths and mechanical interfaces. - [eda-board-3d-comparison](../skills/eda-board-3d-comparison/SKILL.md): Compare original and redesigned PCB assemblies in the native EDA 3D viewer. - [eda-design-summary-video](../skills/eda-design-summary-video/SKILL.md): Make a narrated evidence-based video of PCB placement, routing, validation and native 3D comparison.++## Motor power stages and precision shunt pickup++- [eda-motor-driver-layout](../skills/eda-motor-driver-layout/SKILL.md): ESC, H-bridge and inverter placement and copper review.+- [eda-kelvin-current-sense](../skills/eda-kelvin-current-sense/SKILL.md): preserve Kelvin sense paths through pours and layer transitions.+- [eda-end-to-end-layout](../skills/eda-end-to-end-layout/SKILL.md): keep each engine's own placement through routing and copper iteration.

@@ -42,4 +42,4 @@ Publish actual source, configuration, input/output manifests, native results, ti  - [TI motor-driver layout](https://www.ti.com/lit/an/slva959b/slva959b.pdf): power loops, conductor paths, returns and thermal layout. - [TI current-sense layout](https://www.ti.com/document-viewer/lit/html/SSZTAD8/GUID-B8989FC6-7E3F-4B21-8E84-7390293FB0EF): preserving dedicated sense traces against unintended plane connections.-- [Astra ESC source and limitations](../../docs/examples/astra-esc/README.md).+- [Astra ESC source and limitations](https://wiki.adom.inc/adom/eda-engineering/files/docs/examples/astra-esc/README.md).

@@ -0,0 +1,25 @@+---+name: eda-kelvin-current-sense+description: Use when placing or routing shunts and current-sense amplifiers, or reviewing pours near Kelvin sense traces, including a sense return named GND and sense vias crossing copper planes.+---+Parent skill: eda-engineering++# Preserve the measurement path through final copper fill++Source: [TI SSZTAD8, Vijay Choudhary, March 2017, differential current-sense routing, net ties and polygon keepouts](https://www.ti.com/document-viewer/lit/html/SSZTAD8/GUID-B8989FC6-7E3F-4B21-8E84-7390293FB0EF). Its example uses LM5175 CS/CSG; identify the equivalent pins on the actual device instead of copying those names.++## Decisions from the TI article++Route both sense conductors from the intended shunt pickup points to the sensing inputs, even when one conductor shares the GND net name. A general ground-plane connection is not automatically an equivalent measurement return.++Protect the pair during the pour-finishing stage. A previously correct sense trace can acquire an unwanted connection anywhere along its length when same-net ground copper fills around it.++Use an appropriate net-tie scheme or copper-pour keepout to preserve the intended path. With a net tie, the section still named GND also needs protection. With keepouts, protect the entire route and every relevant copper layer around a through-via; a top-only cutout leaves inner-plane connections possible. Inspect the filled result, not just the trace centerlines. See the article's Figures 2–5.++## Execute and report++Build a pad-level table: shunt terminal, sense-input pin, power-current connection, intended pickup location, and permitted plane connection. Check the schematic and actual pad/net assignments before editing. A net-tie implementation changes connectivity representation and must be kept consistent between schematic, PCB and validation; do not silently rename nets to satisfy DRC.++At placement, route completion and final refill, inspect the two pickup paths and all via annuli on every copper layer. Re-run this check after copper expansion or rerouting. Record any unexpected same-net contact as a failed measurement-path check even when native DRC reports no error.++Deliver annotated pickup/return geometry, chosen keepout or net-tie treatment, native validation and unresolved device/filter requirements. Use the actual amplifier datasheet for filtering, common-mode range, bandwidth and input limits; this article is not a generic filter-design prescription. For the surrounding power stage, read [motor-driver layout](../eda-motor-driver-layout/SKILL.md).

@@ -0,0 +1,27 @@+---+name: eda-motor-driver-layout+description: Use when placing or reviewing an ESC, H-bridge, inverter or motor-driver PCB, especially MOSFET power loops, gate returns, bypass capacitors, thermal copper and multilayer vias.+---+Parent skill: eda-engineering++# Motor-driver placement and copper review++Read the relevant sections of [TI SLVA959B, Best Practices for Board Layout of Motor Drivers, revision B, October 2021](https://www.ti.com/lit/an/slva959b/slva959b.pdf). This is a practical review entrypoint, not a substitute for the selected driver's datasheet.++## Decisions from the TI guide++- Separate noisy power circuitry from sensitive circuitry by placement and return-path planning. Preserve useful reference continuity; do not automatically split ground because analog and digital nets coexist. See section 1.+- Give the actual thermal-pad net a continuous spreading path. Inspect narrow exits, relief spokes and via connections, not only pour area. Respect package and assembly requirements. See sections 2–3.+- Place vias so their clearances do not sever return planes. Size interlayer paths for their load; the example via table is not a universal current rating. See section 3.+- Keep gate loops short, with the appropriate source/switch reference nearby. Place driver support capacitors at their corresponding pins. See sections 4–5.+- Put local ceramic bypass capacitors at the switching-current loop and bulk storage near the supply entry. Evaluate the complete supply-and-return loop. See section 5.+- Choose MOSFET orientation from its real pinout and resulting power paths. Review any dedicated drain-sense connection independently of the broad supply pour. See section 6.+- Treat current-sense routing as a separate precision path. See section 7 and [Kelvin current-sense](../eda-kelvin-current-sense/SKILL.md).++## Execute and report++Use this at three checkpoints: before accepting placement, before occupying power corridors with signals, and after native copper refill. Record each finding as: actual refs/pads, layer, observed geometry, consequence, proposed change, and verification result. Make authorized changes through the selected CAD workflow; do not invent unavailable bridge verbs.++Read [end-to-end layout](../eda-end-to-end-layout/SKILL.md) for provenance and reroute iteration, and [copper ablation](../eda-copper-ablation/SKILL.md) for retention objectives. A motor-driver example's capacitor value, gate width, via dimensions or layer stack is not a default for another board.++Deliver a loop/return map, unresolved layout findings, native DRC/connectivity before and after changes, and the operating/stackup assumptions behind any electrical or thermal claim. Passing DRC alone does not close an unverified power-path finding.