EDA Skillpack
Public Made by Adomby adom
All skills for all EDA capabilities across the Adom ecosystem.
d08db97
23d ago
name: eda-end-to-end-layout description: Carry an independently generated PCB placement through routing, power and thermal copper planning, ablation-aware retention and native validation. Use for complete AI board layouts and fair engine comparisons; preserve design provenance and distinguish a worked-example planner from a reusable router.
Parent skill: eda-engineering
Establish the experiment and its provenance
Record the common schematic/netlist, BOM and footprint identities, fixed interfaces, outline, stackup, manufacturing profile and operating conditions. Hash inputs. For an end-to-end engine comparison, each engine must generate its own movable-part placement, routes and pours. Do not switch to another engine's placed fixture between stages. A shared-placement routing benchmark is a different experiment: label it explicitly, never substitute it for an end-to-end result.
Preserve stage artifacts and a manifest linking each output to the actual input hash and planner revision. A previously verified placement from the same engine can be replayed or continued with its original provenance and accounting; call replay a replay. Never silently describe reused coordinates as newly calculated placement. Strip inherited route and zone geometry from a starting fixture, except common planes or mechanically constrained geometry explicitly allowed by the experiment.
Plan useful copper before filling the routing corridors
Read the electrical-routing, thermal-bottlenecks and copper-ablation skills. Determine current paths and returns, actual continuous/peak loads and duty, voltage, layer copper thickness, via plating assumptions, cooling conditions and temperature limits. A sense amplifier's full-scale current is not the board's current rating. Preserve manufacturer constraints and stricter electrical rules. Continue independent work while missing load specifications are resolved; label provisional analysis.
Place connectors, power devices, bulk/decoupling capacitors, shunts, drivers and sense amplifiers to reserve short, wide power paths and compact switching loops. Keep Kelvin sense takeoffs at the intended shunt terminals; a ground-net name does not authorize merging a dedicated sense path indiscriminately into a power-return pour. Assign each exposed pad to its actual net. Reserve thermal-via and spreading regions before signal routing blocks them.
Classify each net: quiet supply, power return, high-dv/dt switching node, gate drive, current sense, analog/feedback, clock/differential or ordinary signal. Choose copper geometry for the function. A switching node still needs sufficient conductor cross-section; constrain unnecessary area and overlap rather than applying a blanket prohibition on polygons. More grounded copper does not automatically cause a ground loop, and splitting a reference plane can worsen return paths. Review the actual current loops and reference continuity.
Iterate placement, routing and native pours
- Validate placement and fixed-interface preservation. Minimize critical loop geometry as well as wire length. A low ratsnest metric alone is insufficient.
- Route critical escapes and sensitive paths while preserving the planned power and thermal regions. Use the selected CAD bridge and native undo/validation mechanisms. Keep the actual net identity and footprint pad geometry authoritative.
- Build net-assigned regions on each usable copper layer. Select priorities, clearances, neck widths, pad connections, stitching/thermal vias and keepouts from this board's rules. Do not copy numerical gaps or expansion steps from an example as universal defaults.
- Refill natively. Inspect connected geometry, not zone outlines. Check the narrowest necks, pad entrances, thermal spokes, via arrays, connector transitions, return continuity, isolated islands and layer-to-layer transitions.
- Where a signal route cuts a useful power/thermal corridor, evaluate moving the route or relocating the obstructing component. Refill and revalidate every accepted change. Compare electrical and thermal consequences, not merely copper area.
- Retain additional copper for ablation only where electrical behavior and fabrication permit. Do not turn every signal into a broad pour. Keep sensitive-node, antenna, isolation and impedance keepouts. Floating retention requires an explicit process/electrical decision and separate reporting.
- Stop iterating when requirements are met or a documented constraint prevents them, not after an arbitrary number of expansion rounds. Preserve rejected candidates and reasons.
On two-layer boards, route and return copper compete on the same two surfaces. On four or more layers, account for actual plane assignments, dielectric spacing, copper thickness and interlayer vias. Do not partition a reference plane or change stackup solely to increase retained area. Analyze each layer and the connected multilayer path.
Evidence and acceptance
Require zero new native DRC errors and zero unconnected items, with inherited violations identified by type and affected item IDs. Report placement, routing, filled copper and electrical qualification separately. DRC success and copper area do not prove current capacity, temperature or signal integrity.
Measure unioned copper per net and layer inside the usable outline, including tracks/pads/vias and filled zones without double-counting. Subtract drill voids; report islands separately. Compare material-to-remove against the same board before added pours. Area reduction is not a measured machining-time reduction. Report bottleneck widths, copper thickness, via count/plating assumptions and estimated resistance/drop/losses where justified. Validate simulation meshes and boundary conditions before claiming current-density or thermal results.
Publish actual source, configuration, input/output manifests, native results, timestamps, costs and failed attempts through the owning shared project. Report bridge defects to its maintainer with reproduction and evidence so fixes ship to all Adom users; a private executable is not distribution. Skills are reusable guidance; a hardcoded board demo must be labeled and tested before it becomes a generic tool.
Sources and example
- TI motor-driver layout: power loops, conductor paths, returns and thermal layout.
- TI current-sense layout: preserving dedicated sense traces against unintended plane connections.
- Astra ESC source and limitations.
---
name: eda-end-to-end-layout
description: Carry an independently generated PCB placement through routing, power and thermal copper planning, ablation-aware retention and native validation. Use for complete AI board layouts and fair engine comparisons; preserve design provenance and distinguish a worked-example planner from a reusable router.
---
Parent skill: eda-engineering
# Establish the experiment and its provenance
Record the common schematic/netlist, BOM and footprint identities, fixed interfaces, outline, stackup, manufacturing profile and operating conditions. Hash inputs. For an end-to-end engine comparison, each engine must generate its own movable-part placement, routes and pours. Do not switch to another engine's placed fixture between stages. A shared-placement routing benchmark is a different experiment: label it explicitly, never substitute it for an end-to-end result.
Preserve stage artifacts and a manifest linking each output to the actual input hash and planner revision. A previously verified placement from the same engine can be replayed or continued with its original provenance and accounting; call replay a replay. Never silently describe reused coordinates as newly calculated placement. Strip inherited route and zone geometry from a starting fixture, except common planes or mechanically constrained geometry explicitly allowed by the experiment.
# Plan useful copper before filling the routing corridors
Read the electrical-routing, thermal-bottlenecks and copper-ablation skills. Determine current paths and returns, actual continuous/peak loads and duty, voltage, layer copper thickness, via plating assumptions, cooling conditions and temperature limits. A sense amplifier's full-scale current is not the board's current rating. Preserve manufacturer constraints and stricter electrical rules. Continue independent work while missing load specifications are resolved; label provisional analysis.
Place connectors, power devices, bulk/decoupling capacitors, shunts, drivers and sense amplifiers to reserve short, wide power paths and compact switching loops. Keep Kelvin sense takeoffs at the intended shunt terminals; a ground-net name does not authorize merging a dedicated sense path indiscriminately into a power-return pour. Assign each exposed pad to its actual net. Reserve thermal-via and spreading regions before signal routing blocks them.
Classify each net: quiet supply, power return, high-dv/dt switching node, gate drive, current sense, analog/feedback, clock/differential or ordinary signal. Choose copper geometry for the function. A switching node still needs sufficient conductor cross-section; constrain unnecessary area and overlap rather than applying a blanket prohibition on polygons. More grounded copper does not automatically cause a ground loop, and splitting a reference plane can worsen return paths. Review the actual current loops and reference continuity.
# Iterate placement, routing and native pours
1. Validate placement and fixed-interface preservation. Minimize critical loop geometry as well as wire length. A low ratsnest metric alone is insufficient.
2. Route critical escapes and sensitive paths while preserving the planned power and thermal regions. Use the selected CAD bridge and native undo/validation mechanisms. Keep the actual net identity and footprint pad geometry authoritative.
3. Build net-assigned regions on each usable copper layer. Select priorities, clearances, neck widths, pad connections, stitching/thermal vias and keepouts from this board's rules. Do not copy numerical gaps or expansion steps from an example as universal defaults.
4. Refill natively. Inspect connected geometry, not zone outlines. Check the narrowest necks, pad entrances, thermal spokes, via arrays, connector transitions, return continuity, isolated islands and layer-to-layer transitions.
5. Where a signal route cuts a useful power/thermal corridor, evaluate moving the route or relocating the obstructing component. Refill and revalidate every accepted change. Compare electrical and thermal consequences, not merely copper area.
6. Retain additional copper for ablation only where electrical behavior and fabrication permit. Do not turn every signal into a broad pour. Keep sensitive-node, antenna, isolation and impedance keepouts. Floating retention requires an explicit process/electrical decision and separate reporting.
7. Stop iterating when requirements are met or a documented constraint prevents them, not after an arbitrary number of expansion rounds. Preserve rejected candidates and reasons.
On two-layer boards, route and return copper compete on the same two surfaces. On four or more layers, account for actual plane assignments, dielectric spacing, copper thickness and interlayer vias. Do not partition a reference plane or change stackup solely to increase retained area. Analyze each layer and the connected multilayer path.
# Evidence and acceptance
Require zero new native DRC errors and zero unconnected items, with inherited violations identified by type and affected item IDs. Report placement, routing, filled copper and electrical qualification separately. DRC success and copper area do not prove current capacity, temperature or signal integrity.
Measure unioned copper per net and layer inside the usable outline, including tracks/pads/vias and filled zones without double-counting. Subtract drill voids; report islands separately. Compare material-to-remove against the same board before added pours. Area reduction is not a measured machining-time reduction. Report bottleneck widths, copper thickness, via count/plating assumptions and estimated resistance/drop/losses where justified. Validate simulation meshes and boundary conditions before claiming current-density or thermal results.
Publish actual source, configuration, input/output manifests, native results, timestamps, costs and failed attempts through the owning shared project. Report bridge defects to its maintainer with reproduction and evidence so fixes ship to all Adom users; a private executable is not distribution. Skills are reusable guidance; a hardcoded board demo must be labeled and tested before it becomes a generic tool.
# Sources and example
- [TI motor-driver layout](https://www.ti.com/lit/an/slva959b/slva959b.pdf): power loops, conductor paths, returns and thermal layout.
- [TI current-sense layout](https://www.ti.com/document-viewer/lit/html/SSZTAD8/GUID-B8989FC6-7E3F-4B21-8E84-7390293FB0EF): preserving dedicated sense traces against unintended plane connections.
- [Astra ESC source and limitations](https://wiki.adom.inc/adom/eda-engineering/files/docs/examples/astra-esc/README.md).