EDA Skillpack
Public Made by Adomby adom
All skills for all EDA capabilities across the Adom ecosystem.
9458d54
28d ago
name: eda-independent-reroute-comparison description: Re-route an existing hand-routed board independently with your own planner and compare it fairly against the original (or another AI's run) with native baselines, a proven strip, diagnostic rule copies, native DRC on the actual replay, and a side-by-side net-highlight video. Use when asked to "route this board from scratch and compare".
Parent skill: eda-engineering
Independent re-route and fair comparison
Worked example with all evidence: Fable 5.1 vs Adonis on the BQ25792 charger.
Identity and inputs first
Record who is doing the work from the environment, not from the prompt: provider and model as the AI UI reports them, reasoning setting, date, machine (bridge target hostname), CAD version and bridge version. Pin the source: wiki page and commit, file hash on every copy (shared container, wiki clone, host staging), and the sanity counts (parts, nets, pads, copper layers, outline). If any hash differs, say so before calling the comparison identical. Use a stable, unique bridge caller name and work in your own directory and branch.
Baselines before touching anything
Open the untouched original natively and record its routing state and native DRC. Then record the inherited rule set separately: an all-object same-net spacing rule can account for almost every error (1604 of 1611 on the example). Make diagnostic copies of BOTH the reference and the candidate that disable ONLY that named rule; never weaken another rule. Then strip a copy natively: display every copper layer (RIPUP acts on displayed layers only), rip up all nets, refill, export, and prove segments = 0, vias = 0 from the exported file, not from a screenshot. The exported stripped board plus schematic/BOM/manufacturer data is the planner's only geometry input; the reference's traces, another model's plan or its coordinates are not inputs.
Planner
Write or use your own path planner; do not invoke the CAD autorouter, Freerouting, or a bridge-side planner verb if the task is to plan independently. Keep 0/45/90-degree geometry, numeric angle audit, few intentional vias, and an exact-geometry check (shapely or equivalent) separate from the raster the planner searches on. Read eda-fine-pitch-fanout before routing a fine-pitch QFN and eda-native-connectivity-conformance before claiming connectivity. Preserve every failed iteration's log; the retry history is part of the result.
Fair validation
Validate the candidate by injecting it as a file (exact) and by drawing it live (the replay). Report both; a live WIRE/VIA/POLYGON replay can differ from the file (drill class, wire truncation at pad origins, junction splitting). Native refill and native DRC on the actual recorded replay are required; never substitute the file result for the video's board. Report per stage: airwires, errors by rule, warnings, the diagnostic-copy numbers, and the inherited signatures you verified rather than assumed.
Side-by-side net comparison
Record both boards natively with the same fit and layer display, cycling the native highlight (Fusion SHOW ) over every net in the same order; pick the frame with the strongest highlight inside each dwell window; crop to the board; composite left/right with one fact line per side computed from the files (segments, length, width range, layers, vias, pours, airwires). Label the composite as postproduction. Narrate reasoning by net family (input path, switching, output, ground, control, logic, low-current rails) and keep the honest score at the end.
Report
Source hash, model, tools, elapsed planning/routing/validation time, retry counts, completion, segment/via/pour counts, off-angle count, DRC by rule set, unconnected count, copper areas by layer and per net (unioned, drill-subtracted), thermal assumptions and the finish decision, unresolved limits. Include token/cost only if genuinely available. Never call a geometrically connected board production qualified.
---
name: eda-independent-reroute-comparison
description: Re-route an existing hand-routed board independently with your own planner and compare it fairly against the original (or another AI's run) with native baselines, a proven strip, diagnostic rule copies, native DRC on the actual replay, and a side-by-side net-highlight video. Use when asked to "route this board from scratch and compare".
---
Parent skill: eda-engineering
# Independent re-route and fair comparison
Worked example with all evidence: [Fable 5.1 vs Adonis on the BQ25792 charger](../../docs/examples/fable5-bq25792/README.md).
## Identity and inputs first
Record who is doing the work from the environment, not from the prompt: provider and model as the AI UI reports them, reasoning setting, date, machine (bridge target hostname), CAD version and bridge version. Pin the source: wiki page and commit, file hash on every copy (shared container, wiki clone, host staging), and the sanity counts (parts, nets, pads, copper layers, outline). If any hash differs, say so before calling the comparison identical. Use a stable, unique bridge caller name and work in your own directory and branch.
## Baselines before touching anything
Open the untouched original natively and record its routing state and native DRC. Then record the inherited rule set separately: an all-object same-net spacing rule can account for almost every error (1604 of 1611 on the example). Make diagnostic copies of BOTH the reference and the candidate that disable ONLY that named rule; never weaken another rule. Then strip a copy natively: display every copper layer (RIPUP acts on displayed layers only), rip up all nets, refill, export, and prove segments = 0, vias = 0 from the exported file, not from a screenshot. The exported stripped board plus schematic/BOM/manufacturer data is the planner's only geometry input; the reference's traces, another model's plan or its coordinates are not inputs.
## Planner
Write or use your own path planner; do not invoke the CAD autorouter, Freerouting, or a bridge-side planner verb if the task is to plan independently. Keep 0/45/90-degree geometry, numeric angle audit, few intentional vias, and an exact-geometry check (shapely or equivalent) separate from the raster the planner searches on. Read [eda-fine-pitch-fanout](../eda-fine-pitch-fanout/SKILL.md) before routing a fine-pitch QFN and [eda-native-connectivity-conformance](../eda-native-connectivity-conformance/SKILL.md) before claiming connectivity. Preserve every failed iteration's log; the retry history is part of the result.
## Fair validation
Validate the candidate by injecting it as a file (exact) and by drawing it live (the replay). Report both; a live WIRE/VIA/POLYGON replay can differ from the file (drill class, wire truncation at pad origins, junction splitting). Native refill and native DRC on the actual recorded replay are required; never substitute the file result for the video's board. Report per stage: airwires, errors by rule, warnings, the diagnostic-copy numbers, and the inherited signatures you verified rather than assumed.
## Side-by-side net comparison
Record both boards natively with the same fit and layer display, cycling the native highlight (Fusion SHOW <net>) over every net in the same order; pick the frame with the strongest highlight inside each dwell window; crop to the board; composite left/right with one fact line per side computed from the files (segments, length, width range, layers, vias, pours, airwires). Label the composite as postproduction. Narrate reasoning by net family (input path, switching, output, ground, control, logic, low-current rails) and keep the honest score at the end.
## Report
Source hash, model, tools, elapsed planning/routing/validation time, retry counts, completion, segment/via/pour counts, off-angle count, DRC by rule set, unconnected count, copper areas by layer and per net (unioned, drill-subtracted), thermal assumptions and the finish decision, unresolved limits. Include token/cost only if genuinely available. Never call a geometrically connected board production qualified.