---
name: eda-multilayer-current-review
description: Review multilayer PCB copper connectivity, matched-net X-ray comparisons and modeled DC current paths. Use for power-path bottlenecks, supply-plane stitching, retained floating copper and current-density overlays in any EDA tool.
---
Parent skill: eda-engineering

# Multilayer X-ray and current-density reviews

Use native, refilled conductor geometry, including net-assigned graphics, pads, tracks, vias and pours. Preserve original and successive candidate boards with hashes and validation evidence. Compare matched nets by pad membership using a common camera, scale and layer orientation. A translucent exported 3D stack is an analysis visualization, not native editor footage.

Show inactive copper at the requested opacity and the selected net opaque across all layers. Distinguish opacity from transparency. Keep layer names and order visible. Read dielectric spacing and copper thickness from the board, and distinguish design-file values from confirmed fabrication specifications. Label any exploded or vertically exaggerated stack, with a true-scale option. Render holes and actual plated interlayer connections; do not draw an electrical connection merely because shapes overlap in projection.

A current-density overlay needs a stated load case and source/sink terminals. Verify populated versus DNP parts, parallel paths, separate grounds, net ties, shunts and Kelvin sense connections. Do not assume every connector carries full load or distribute current equally among layers or device pads without a model that justifies it. Leave unknown-load nets uncolored or present a separately labeled normalized unit-current calculation.

For a coupled-layer DC model, record copper conductivity and temperature, thickness, via drill and plating, layer spacing, terminal boundary conditions, mesh construction and treatment of holes. Unknown via plating requires an explicit provisional assumption and sensitivity analysis. Avoid raster shortcuts across isolation gaps and account for narrow partial cells or refine the mesh. Validate current conservation, power balance and a known rectangular conductor; check convergence for resistance and reported neck metrics. Singular contact/corner peaks and unresolved necks must not be presented as precise physical maxima.

Use consistent units, legends and color limits for matched comparisons. Current density, potential drop and resistive loss are different quantities. None is a measured temperature map or a current rating. State omitted contact/package resistance, switching/transient effects and thermal feedback. Preserve the numerical data and model inputs with the video.

Use findings to revisit supply-plane coverage, return continuity, necks and interlayer connections. More copper on selected nets or fewer vias is not automatically better. Report total conductor retention and displaced reference copper too. Refill and run uncapped native DRC on every accepted revision, compare stricter diagnostic results against the preserved original, and record unresolved electrical qualification limits. Keep example-specific loads and host paths out of the general skill.

When the user explicitly permits orphaned pours for copper ablation, preserve permissible floating islands rather than automatically deleting them. Keep clearance and isolation barriers intact. Report connected copper and floating retention separately. A zone net label does not establish a conducting path: disconnected islands must not carry modeled load current or be presented as connected thermal spreading. Visually distinguish floating islands in net highlights, and omit them from the electrical solve or solve them as unexcited floating conductors without inventing sources.

Do not assume subtracting an island-removed refill from an island-retaining refill gives the exact floating area. Removing a high-priority island can let another net refill the vacated space, changing both sides of the geometric difference. Classify connected components on the actual retained board using native connectivity or an explicitly checked conductor graph through plated holes. State whether connected means a path to any circuit pad or to the active source/sink network; those are different criteria.

After enabling orphan retention, audit supply and reference planes again. A large nominal supply region can be half floating and displace useful connected ground. Prefer connecting useful regions with clearance-checked stitching where a same-net path exists on another layer. Retain the remaining permissible islands for fabrication only. Refill, reclassify and validate after stitching; update the numerical input hash and rendered geometry together. Do not reuse a prior iteration's attractive video or current map on an altered board without proving the modeled conductor geometry is unchanged.

Discover the selected bridge's current export, net-highlight and 3D-view capabilities before choosing a renderer. If the native viewer does not provide the requested opacity or field overlay, use native exported geometry for a separate, labeled analysis artifact. Do not invent a bridge verb or imply that postprocessed X-ray imagery is a native CAD viewer feature. Preserve which work ran through the bridge and which ran in the separate solver or renderer.

Use the selected EDA bridge for native execution and validation. Read `eda-electrical-routing`, `eda-copper-ablation` and `eda-pour-planning-measurement` when their decisions apply. Read the current applicable manufacturer and insulation guidance before making safety claims. Worked-example values are evidence for that example, never defaults for another board.