EDA Skillpack

@@ -37,3 +37,13 @@ Read the [skill](skills/eda-visible-routing/SKILL.md) directly from the wiki. An - [eda-design-summary-video](skills/eda-design-summary-video/SKILL.md): Make a narrated evidence-based video of PCB placement, routing, validation and native 3D comparison.  These skills are published as readable source. The installable package is still pending; read the files directly through the wiki rather than assume an installation command succeeds.++## KiCad worked example: multilayer power and copper retention++The [Codex Astra + KiCad guide](https://wiki.adom.inc/adom/kicad-bridge/files/docs/CODEX-ASTRA.md) follows simple live traces through a public four-layer BMS. The later [BMS X-ray and current review](https://wiki.adom.inc/adom/codex/files/docs/BMS-XRAY-REVIEW.md) compares matched nets, revisits power vias and supply-plane stitching, and separates floating copper retention from useful electrical copper.++![Matched-net BMS supply comparison from exported native geometry](https://wiki.adom.inc/api/pages/adom/codex/files/screenshots/bms-xray-supply.png)++The general lessons are in [eda-multilayer-current-review](skills/eda-multilayer-current-review/SKILL.md), linked from the copper-ablation and pour-measurement skills. They apply to any AI and EDA tool: explicit load terminals, native refilled geometry, conductor connectivity, numerical verification, honest legends and validation of the actual saved revision. These are analysis graphics, not a claim that every bridge has a native X-ray or current-field verb. Device-specific values and unresolved checks remain with the worked example.++Read these skills directly from the source while the EDA Skillpack's installable release awaits its reviewed hero. Adding source guidance does not update already-installed packages or instructions loaded in an existing AI conversation.

@@ -12,6 +12,8 @@ Start with the [skill directory](references/skill-directory.md) to find the rele  The bundled shared skills are: +- [Multilayer current review](skills/eda-multilayer-current-review/SKILL.md): native conductor connectivity, matched-net X-ray comparisons, explicit DC load cases and floating-copper accounting.+ - [Visible routing and copper optimization](skills/eda-visible-routing/SKILL.md): live routing, clean bends, electrical priorities, copper expansion and thermal review. - [Electrical routing](skills/eda-electrical-routing/SKILL.md): current budgets, route geometry and copper-pour decisions. - [Thermal bottlenecks](skills/eda-thermal-bottlenecks/SKILL.md): review connected heat-spreading paths and suitable reroutes.

@@ -22,6 +22,7 @@ Read the entry for the user's task, then the owning package's current skill. The | Fine-pitch QFN escapes and dog-bone fan-out | [eda-fine-pitch-fanout](../skills/eda-fine-pitch-fanout/SKILL.md) | | Pour regions, stitching, expansion and copper measurement | [eda-pour-planning-measurement](../skills/eda-pour-planning-measurement/SKILL.md) | | Worked example with evidence: BQ25792 independent re-route vs original | [docs/examples/fable5-bq25792](../docs/examples/fable5-bq25792/README.md) |+| Multilayer current paths, X-ray comparison and floating-copper classification | [eda-multilayer-current-review](../skills/eda-multilayer-current-review/SKILL.md) | | Broader EDA application discovery | [Adom EDA hub](https://wiki.adom.inc/adom/eda) |  A future Adom Molecule Skillpack can be cross-linked here when its owning package and entrypoint are established. Its packaging is undecided; no dependency or speculative install command is declared. Fusion, KiCad and Altium may similarly organize tool-specific skillpacks within their bridges.

@@ -31,3 +31,7 @@ Compare fresh native DRC and connectivity with the baseline under the same rule  If an inherited rule is inconsistent with intended connectivity, diagnose it on comparison copies, disclose the exact change, and retain the unmodified reference. Never hide violations by suppressing rules to improve the video result. ++## Multilayer connectivity and current review++Use [eda-multilayer-current-review](../eda-multilayer-current-review/SKILL.md) for the conductor graph, source/sink model and supply/reference stitching audit. Distinguish total retained copper, copper connected to any circuit pad, and copper participating in the selected load path. Removing islands and refilling can let another net occupy the space, so subtracting two refill areas is not an exact floating-area measurement. Revalidate the actual retained board after stitching and report its remaining island warnings and opens separately from diagnostic copies.

@@ -0,0 +1,29 @@+---+name: eda-multilayer-current-review+description: Review multilayer PCB copper connectivity, matched-net X-ray comparisons and modeled DC current paths. Use for power-path bottlenecks, supply-plane stitching, retained floating copper and current-density overlays in any EDA tool.+---+Parent skill: eda-engineering++# Multilayer X-ray and current-density reviews++Use native, refilled conductor geometry, including net-assigned graphics, pads, tracks, vias and pours. Preserve original and successive candidate boards with hashes and validation evidence. Compare matched nets by pad membership using a common camera, scale and layer orientation. A translucent exported 3D stack is an analysis visualization, not native editor footage.++Show inactive copper at the requested opacity and the selected net opaque across all layers. Distinguish opacity from transparency. Keep layer names and order visible. Read dielectric spacing and copper thickness from the board, and distinguish design-file values from confirmed fabrication specifications. Label any exploded or vertically exaggerated stack, with a true-scale option. Render holes and actual plated interlayer connections; do not draw an electrical connection merely because shapes overlap in projection.++A current-density overlay needs a stated load case and source/sink terminals. Verify populated versus DNP parts, parallel paths, separate grounds, net ties, shunts and Kelvin sense connections. Do not assume every connector carries full load or distribute current equally among layers or device pads without a model that justifies it. Leave unknown-load nets uncolored or present a separately labeled normalized unit-current calculation.++For a coupled-layer DC model, record copper conductivity and temperature, thickness, via drill and plating, layer spacing, terminal boundary conditions, mesh construction and treatment of holes. Unknown via plating requires an explicit provisional assumption and sensitivity analysis. Avoid raster shortcuts across isolation gaps and account for narrow partial cells or refine the mesh. Validate current conservation, power balance and a known rectangular conductor; check convergence for resistance and reported neck metrics. Singular contact/corner peaks and unresolved necks must not be presented as precise physical maxima.++Use consistent units, legends and color limits for matched comparisons. Current density, potential drop and resistive loss are different quantities. None is a measured temperature map or a current rating. State omitted contact/package resistance, switching/transient effects and thermal feedback. Preserve the numerical data and model inputs with the video.++Use findings to revisit supply-plane coverage, return continuity, necks and interlayer connections. More copper on selected nets or fewer vias is not automatically better. Report total conductor retention and displaced reference copper too. Refill and run uncapped native DRC on every accepted revision, compare stricter diagnostic results against the preserved original, and record unresolved electrical qualification limits. Keep example-specific loads and host paths out of the general skill.++When the user explicitly permits orphaned pours for copper ablation, preserve permissible floating islands rather than automatically deleting them. Keep clearance and isolation barriers intact. Report connected copper and floating retention separately. A zone net label does not establish a conducting path: disconnected islands must not carry modeled load current or be presented as connected thermal spreading. Visually distinguish floating islands in net highlights, and omit them from the electrical solve or solve them as unexcited floating conductors without inventing sources.++Do not assume subtracting an island-removed refill from an island-retaining refill gives the exact floating area. Removing a high-priority island can let another net refill the vacated space, changing both sides of the geometric difference. Classify connected components on the actual retained board using native connectivity or an explicitly checked conductor graph through plated holes. State whether connected means a path to any circuit pad or to the active source/sink network; those are different criteria.++After enabling orphan retention, audit supply and reference planes again. A large nominal supply region can be half floating and displace useful connected ground. Prefer connecting useful regions with clearance-checked stitching where a same-net path exists on another layer. Retain the remaining permissible islands for fabrication only. Refill, reclassify and validate after stitching; update the numerical input hash and rendered geometry together. Do not reuse a prior iteration's attractive video or current map on an altered board without proving the modeled conductor geometry is unchanged.++Discover the selected bridge's current export, net-highlight and 3D-view capabilities before choosing a renderer. If the native viewer does not provide the requested opacity or field overlay, use native exported geometry for a separate, labeled analysis artifact. Do not invent a bridge verb or imply that postprocessed X-ray imagery is a native CAD viewer feature. Preserve which work ran through the bridge and which ran in the separate solver or renderer.++Use the selected EDA bridge for native execution and validation. Read `eda-electrical-routing`, `eda-copper-ablation` and `eda-pour-planning-measurement` when their decisions apply. Read the current applicable manufacturer and insulation guidance before making safety claims. Worked-example values are evidence for that example, never defaults for another board.

@@ -18,3 +18,7 @@ Parent skill: eda-engineering # Measurement and thermal claims - Report per layer: fixed copper only, reference, candidate predicted, candidate native; and per net: connected area and island area, drill-subtracted, unioned. - For mask-versus-bare decisions use a documented plate calculation with convection and radiation (35 um copper, fixed source temperature, finish emissivity: mask about 0.9, ENIG/HASL about 0.1-0.15). Removing mask over bright finishes lowers radiated heat; it is not a free win. Label results as comparisons at a fixed source temperature, not measured temperatures or a rating, and list what the model omits (package, vias, FR4, narrow pin escapes, enclosure).++## Multilayer connectivity and current review++Use [eda-multilayer-current-review](../eda-multilayer-current-review/SKILL.md) for the conductor graph, source/sink model and supply/reference stitching audit. Distinguish total retained copper, copper connected to any circuit pad, and copper participating in the selected load path. Removing islands and refilling can let another net occupy the space, so subtracting two refill areas is not an exact floating-area measurement. Revalidate the actual retained board after stitching and report its remaining island warnings and opens separately from diagnostic copies.