---
name: eda-native-connectivity-conformance
description: Make generated copper count as connected in Fusion Electronics / EAGLE - endpoint rules for wires, pads, vias and package copper, same-signal via clearance, drill classes, live-command pitfalls - so the native ratsnest reports zero airwires. Use before validating or replaying planner output in Fusion.
---
Parent skill: eda-engineering

# Native connectivity is endpoint-based, not overlap-based

Measured on Fusion 2705 with the routing bridge (fusion_routing_state / fusion_routing_drc), BQ25792 example, 2026-09-07. An exact-geometry checker that treats any copper overlap as a connection reported zero split nets while Fusion showed 80 airwires. The rules that took it to zero:

- Two wires of the same signal connect only at a coincident endpoint (a T-junction needs a vertex on the wire being joined; split it there).
- A wire connects to an SMD pad when an endpoint lies inside the pad polygon; crossing a pad without an endpoint does not connect. Split wires at every same-net pad they pass over.
- A wire connects to a through-hole pad or a via only at its origin. An endpoint anywhere else inside the ring is an airwire; extend to the centre with axis-aligned pieces.
- Package copper (polygonshape tabs such as MOSFET drain pads) does not connect a wire by overlap; end the wire on one of the tab's anchor pads or plated holes.
- Pours connect to same-net pads/vias by thermals or solid fills after refill; an island (no via, no pad) is dropped with orphans off and must not be counted as heatsinking.
- Keep a native oracle loop: read the tool's own airwire list (start/end points), add short axis-aligned joiners between the endpoints, refill, re-read; three rounds usually close what geometry alone misses.

# Rules that bite generated vias and pours
- Fusion's default rule set has same-signal clearances: SMD-to-via, SMD-to-pad, SMD-to-SMD 0.1 mm. A stitching or dog-bone via must keep 0.1 mm from its own SMD pad or sit fully inside it.
- Two vias of one net closer than the drill distance raise Drill Clearance; dedupe overlapping same-net vias when the net stays connected.
- Equal-rank polygons of different signals must not overlap; the importer may not honour the rank attribute, so keep power-pour outlines geometrically disjoint with a real gap and let ground take the remainder.
- The inherited all-object "Same-net track spacing" rule flags adjacent same-net pin stubs at 0.4 mm pitch; classify it separately with a diagnostic copy that disables only that rule.

# Live command pitfalls (drawing through the CAD command line)
- VIA takes a diameter only; the drill comes from CHANGE DRILL. Emit CHANGE DRILL per via class or every signal via grows to the power drill's minimum ring and violates its neighbours (0.4 mm vias became 0.5 mm on the example replay).
- WIRE drawn into a pad origin can be truncated at the pad boundary by the tool; verify with the routing state after the replay, not from the command acceptance.
- RIPUP acts only on displayed layers; DISPLAY all copper layers before stripping.
- Coordinates given on the command line are not snapped to the grid, so grid is not the cause of endpoint mismatches; check junction handling instead.
- DRC error entries may carry x/y instead of a single point field; count entries by code rather than trusting summary totals.