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John Lauer Index reusable placement and 3D review skills with clear discovery entrypoints ff7a528 28d ago

name: eda-board-3d-comparison description: >- Compare original and redesigned PCB assemblies in the native EDA 3D viewer. Use when asked to show my board in 3D, compare component placement, inspect stacked modules, explain symmetry or check assembly access. user-invocable: true

Parent skill: eda-engineering

Native 3D placement comparison

Create or update native 3D derivatives from the verified original and candidate 2D boards. Confirm document identities and current source linkage; preserve accepted 2D geometry. Verify that the viewer contains the actual board and populated package models. Identify missing/placeholder models. An external visualization is not evidence that the requested native viewer worked.

Inspect application state after slow generation or timeout before retrying. A new 3D document can exist even when the transport reply timed out. Save newly generated task documents promptly. In Fusion, consult its bridge's 3D/electronics and cloud-save skills; discover fusion_show_3d_board, fusion_view and document schemas rather than assuming command support.

Record both complete assemblies from the same board orientation, camera path and scale. Automatic fit can produce different scales because invisible geometry or assembly extents differ. Use identical explicit orthographic camera settings for comparative top views, and verify the recorded frames. Include oblique views to show heights and stacked modules.

When daughterboards obscure the main PCB, temporarily hide the corresponding assembly occurrences in BOTH copies. State that visibility is changed for inspection, not that parts are removed. Preserve the original visibility map, including already-hidden objects, and restore it afterward. Do not blindly turn every occurrence on. Recheck and save the restored assembly state.

Explain actual coordinate/rotation differences in functional groups. Pair full-board context with closeups or editorial callouts. Label overlays so they are not confused with native selection, simulation or measured clearance. Acknowledge symmetry, grouping, assembly access, increased vias and other disadvantages, rather than claiming every new placement is superior.

Look for daughterboard/base-component collisions, connector/wiring access, mating orientation, contact alignment, standoffs, pin lengths, edge clearance and service access. Visual inspection can reveal concerns, but use native interference checks, tolerances and approved mechanical envelopes before declaring fit. Missing models and unspecified pin/press-fit tolerances remain open items. Thermal conclusions need electrical losses and cooling assumptions; 3D appearance alone is not a thermal result.

Preserve both native derivatives, source snapshots, camera settings, model inventory and comparison evidence. Close only completed task scratch documents after saving; leave other work alone.