---
name: eda-placement-routing-review
description: >-
  Coordinate an independent PCB placement, trace routing, native 3D review and narrated comparison. Use when asked to place and route my board, start from an empty board, compare AI and human placement, or show the whole PCB design process.
user-invocable: true
---
Parent skill: eda-engineering

# Placement, routing and review

Use this AI-neutral workflow with the user's selected EDA bridge. Read `eda-component-placement`,
`eda-visible-routing`, `eda-board-3d-comparison` and, when a video is requested,
`eda-design-summary-video`. Consult the EDA skill directory for tool-owned commands and
Molecule/manufacturing guidance. These are methods, not a bundled optimizer or a promise of
automatic signoff.

1. Discover the live desktop, CAD version, bridge capabilities, active document and concurrent
ownership. Preserve intentional development pins. Save an immutable reference and create a uniquely
named task copy before edits. 2. Ask which manufacturer/process the user wants. Load its actual rule
profile, read it back, and keep stricter user/electrical constraints. Ask about voltage/transients,
current, stackup/copper and cooling when needed for power or thermal claims. Missing inputs do not
prevent a labelled placement study; they prevent qualification claims. 3. Establish outline,
mounting/mating patterns, connector access, stackable modules, keepouts and mechanical constraints.
Use current domain-owned standards, not a remembered demo dimension. 4. Record the original. When
the task requests fresh placement, strip routes/vias/pours from the copy, move eligible components
off-board, then inspect native counts/positions. Preserve nets, pads, devices and approved outline.
Show proof of the initial state. 5. Calculate placement and routing candidates from the actual
netlist/footprints. Distinguish fresh calculation from replay of a saved solution. Save rejected
candidates and reasons. Check footprint bodies, pads, rotations and routing feasibility before
showing an accepted candidate as final. 6. Apply accepted placement and routes visibly in bounded
groups. Preserve checkpoints and call/revision logs. Show short progress explanations with the
application's existing status surface. Do not present private internal reasoning; show design
criteria, measurable checks and accepted decisions. 7. Refill and run native DRC on the actual
replay. Verify placement, netlist, copper per net/layer, via identity and final native connectivity.
Same-net copper overlap is not always a native junction. Consult native-connectivity-conformance and
fine-pitch-fanout skills. 8. Compare native 3D assemblies and explain actual moves, including
disadvantages. Save documents, restore temporary visibility changes and make a concise narrated
summary when requested.

Acceptance evidence includes the original/candidate source, applied rule profile,
interface/placement audit, native DRC, actual geometry read-back, 3D model/visibility state, and
video provenance. Report baseline and introduced issues separately. A clean DRC is not ERC,
synchronized schematic/PCB, current capacity, thermal performance, mechanical fit or CAM
qualification. Say which remain open.