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EDA Skillpack
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John Lauer
Add shared multilayer current review and connected copper lessons from KiCad exploration
9b9c414
28d ago
name: eda-pour-planning-measurement description: Plan power and ground pours from a placement, connect them across layers with stitching and island vias, run a bounded expansion pass, and measure connected copper honestly (unions, drill voids, islands excluded, native layer images) with reassigned ground reported. Use after routing and before thermal claims.
Parent skill: eda-engineering
Regions, ranks and connectivity
- Define one region per power net and layer from the placement (bulk caps, connector nests, FET tabs); ground takes every layer at lowest priority. Keep power-region outlines geometrically disjoint (subtract earlier regions with a gap of at least the isolate plus outline width) instead of relying on polygon rank, which the importer may ignore.
- A thermal pad or tab is not necessarily ground: on the example the MOSFET tabs are VAC1, VBUS, VAC2 and VBAT and their seven plated holes carry the bottom pours to the tabs; the charger QFN footprint has no exposed pad at all, so its heat leaves through the power pins into SYS, PMID, VBUS, BAT and ground copper.
- Never pour high-dv/dt switch nodes; keep them compact.
- A bottom pour connects only if a same-net via or plated hole lands inside it. Add stitching vias next to bulk-capacitor pads with an exact legality check (0.1 mm to any SMD pad, drill spacing, other-net clearance), and island vias where a bottom island lies under the same net's connected top pour. Drop any via the native ratsnest still reports as open.
- Predicted fill = region minus other-net copper dilated by the isolate, opened by the minimum neck, islands removed. Validate the prediction against the CAD's own refilled layer images (copper pixels inside the board rectangle); on the example the two agreed within about 3 % per layer.
Expansion pass
- After the initial pours, grow each power region once by a fixed step (1.5 mm) and keep the growth only when its connected area rises and no other power pour loses more than a small threshold; ground absorbs the remainder. A greedy multi-round re-predict loop is too slow on a dense board; one deliberate pass is enough and is explainable.
- Report ground copper reassigned to power nets as a loss, never as new cooling area (bottom ground fell 370 to 345 mm2 on the example).
Measurement and thermal claims
- Report per layer: fixed copper only, reference, candidate predicted, candidate native; and per net: connected area and island area, drill-subtracted, unioned.
- For mask-versus-bare decisions use a documented plate calculation with convection and radiation (35 um copper, fixed source temperature, finish emissivity: mask about 0.9, ENIG/HASL about 0.1-0.15). Removing mask over bright finishes lowers radiated heat; it is not a free win. Label results as comparisons at a fixed source temperature, not measured temperatures or a rating, and list what the model omits (package, vias, FR4, narrow pin escapes, enclosure).
Multilayer connectivity and current review
Use eda-multilayer-current-review for the conductor graph, source/sink model and supply/reference stitching audit. Distinguish total retained copper, copper connected to any circuit pad, and copper participating in the selected load path. Removing islands and refilling can let another net occupy the space, so subtracting two refill areas is not an exact floating-area measurement. Revalidate the actual retained board after stitching and report its remaining island warnings and opens separately from diagnostic copies.
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name: eda-pour-planning-measurement
description: Plan power and ground pours from a placement, connect them across layers with stitching and island vias, run a bounded expansion pass, and measure connected copper honestly (unions, drill voids, islands excluded, native layer images) with reassigned ground reported. Use after routing and before thermal claims.
---
Parent skill: eda-engineering
# Regions, ranks and connectivity
- Define one region per power net and layer from the placement (bulk caps, connector nests, FET tabs); ground takes every layer at lowest priority. Keep power-region outlines geometrically disjoint (subtract earlier regions with a gap of at least the isolate plus outline width) instead of relying on polygon rank, which the importer may ignore.
- A thermal pad or tab is not necessarily ground: on the example the MOSFET tabs are VAC1, VBUS, VAC2 and VBAT and their seven plated holes carry the bottom pours to the tabs; the charger QFN footprint has no exposed pad at all, so its heat leaves through the power pins into SYS, PMID, VBUS, BAT and ground copper.
- Never pour high-dv/dt switch nodes; keep them compact.
- A bottom pour connects only if a same-net via or plated hole lands inside it. Add stitching vias next to bulk-capacitor pads with an exact legality check (0.1 mm to any SMD pad, drill spacing, other-net clearance), and island vias where a bottom island lies under the same net's connected top pour. Drop any via the native ratsnest still reports as open.
- Predicted fill = region minus other-net copper dilated by the isolate, opened by the minimum neck, islands removed. Validate the prediction against the CAD's own refilled layer images (copper pixels inside the board rectangle); on the example the two agreed within about 3 % per layer.
# Expansion pass
- After the initial pours, grow each power region once by a fixed step (1.5 mm) and keep the growth only when its connected area rises and no other power pour loses more than a small threshold; ground absorbs the remainder. A greedy multi-round re-predict loop is too slow on a dense board; one deliberate pass is enough and is explainable.
- Report ground copper reassigned to power nets as a loss, never as new cooling area (bottom ground fell 370 to 345 mm2 on the example).
# Measurement and thermal claims
- Report per layer: fixed copper only, reference, candidate predicted, candidate native; and per net: connected area and island area, drill-subtracted, unioned.
- For mask-versus-bare decisions use a documented plate calculation with convection and radiation (35 um copper, fixed source temperature, finish emissivity: mask about 0.9, ENIG/HASL about 0.1-0.15). Removing mask over bright finishes lowers radiated heat; it is not a free win. Label results as comparisons at a fixed source temperature, not measured temperatures or a rating, and list what the model omits (package, vias, FR4, narrow pin escapes, enclosure).
## Multilayer connectivity and current review
Use [eda-multilayer-current-review](../eda-multilayer-current-review/SKILL.md) for the conductor graph, source/sink model and supply/reference stitching audit. Distinguish total retained copper, copper connected to any circuit pad, and copper participating in the selected load path. Removing islands and refilling can let another net occupy the space, so subtracting two refill areas is not an exact floating-area measurement. Revalidate the actual retained board after stitching and report its remaining island warnings and opens separately from diagnostic copies.