PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
Discover
How an AI finds this repo: the auto-discovery snippet from page.json, self-tested against the live discovery search.
Snippet
Use when the user asks about PCB design rules, DRC limits, fab capabilities, minimum trace width, drill, via or annular ring limits, or wants to load a fab's rules into Fusion, KiCad or Altium.
what is the minimum trace width and drill for JLCPCB vs PCBWay 2 layer?load the JLCPCB 4 layer design rules into my Fusion boardgive me the KiCad custom rules file for OSH Park 2 layerSample prompts: self-test
How this repo ranks when its full trigger set is the query.
Each sample prompt run against the live discovery search. The score is your rank, does the prompt return this repo at the top?
"what is the minimum trace width and drill for JLCPCB vs PCBWay 2 layer?"Compare fab limits
not in results
"load the JLCPCB 4 layer design rules into my Fusion board"Load rules into Fusion
not in results
"give me the KiCad custom rules file for OSH Park 2 layer"KiCad rules for a fab
not in results