PCB Design Rules - Activity

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

Overview Files Skills Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

Latest Releases

No releases yet

Recent Commits

Verification: loaded all six 2L/4L .edru files (InstaPCB, JLCPCB, PCBWay) into a real Fusion board on AdomLapper via drc load, zero dialogs, empty fusion_alerts; confirmed Fusion 2026 accepts .edru and rejects .dru; export of active rules matched the PCBWay record. KiCad 10 enforced jlcpcb-2L.kicad_dru in a discriminating with/without DRC test through the kicad bridge. Screenshots attached. ConfRoomROG was offline; Altium RUL import not verified.

John Lauer · e35f213 · 2d ago

Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read from official capabilities pages on 2026-09-03, Adom InstaPCB house baseline from bundled seed .edru files. Generated Fusion .edru/.dru, KiCad .kicad_dru + board-setup JSON, Altium .RUL, comparison table, SKILL.md with discovery_triggers.

John Lauer · bafc3ce · 2d ago

Initial commit: skill/pcb-design-rules

John Lauer · 01e26bb · 2d ago

Contributors

John Lauer 3 commits