PCB Design Rules - Activity

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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Specify 3rdPartyFab reference/value sizes and face-aware mechanical silkscreen policy

John Lauer · a59b909 · 6d ago

Document 1 oz finished copper standard and 2 oz request option; preserve existing DRC limits

John Lauer · fce5c48 · 9d ago

Silkscreen text minimums: 3rdPartyFab 0.5 mm, JLCPCB 0.8 mm (Adom-tested)

John Lauer · 437f71a · 13d ago

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John Lauer 21 commits