PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
Skills
The skills this repo ships, by tier, each with a quick health read. Install the user skills with:
adom-wiki skills install adom/pcb-design-rulesCanonical PCB fab design rules (DRC) for every popular vendor, one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru files, KiCad .kicad_dru custom rules plus board-setup constraints JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read. This is where Adom bridges load design rules from: fusion_set_design_rules {fab, layers, druPath?} consumes the files on this page. Trigger words: design rules, DRC, JLCPCB rules, load PCBWay rules, InstaPCB rules, drc load, fab capabilities, min trace width, min drill, annular ring, copper clearance, edru, kicad_dru, design rule files by fab.
No dev skills in this repo.
How to build, debug, and test this app. Source-only (dev-skills/), never shipped in the tarball.
No publish skills in this repo.
The app-to-wiki publish glue. Source-only (publish-skills/), never shipped in the tarball.
Health: the size chip is green when right-sized, yellow when getting long, red when the model likely skims it. A green check is a passed preamble/structure signal; an amber mark is a gentle nudge, not a hard failure.