skill

PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

pcbdesign-rulesdrcfabricationjlcpcbpcbwayfusionkicadaltiumedrukicad_dru
Overview Files Skills Discover Packages Releases Dependencies Issues1 Breadcrumbs Pull Requests1 Activity

History of kicad/adom-3rdpartyfab-4L.board-setup.json

6 commits ← Back to file
Specify 3rdPartyFab reference/value sizes and face-aware mechanical silkscreen policy
John Lauer · a59b909 · 5d ago
Document 1 oz finished copper standard and 2 oz request option; preserve existing DRC limits
John Lauer · fce5c48 · 8d ago
Silkscreen text minimums: 3rdPartyFab 0.5 mm, JLCPCB 0.8 mm (Adom-tested)
John Lauer · 437f71a · 12d ago
Rename the 3rd party fab rule packs: adom-3rdpartyfab
John Lauer · 676909d · 14d ago
Use generic 3rd party fab wording
John Lauer · 33b6fc3 · 20d ago
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
John Lauer · bafc3ce · 1mo ago