PCB Design Rules - Commit

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

Overview Files Skills Discover Packages Releases Dependencies Issues1 Breadcrumbs Pull Requests1 Activity

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Use generic 3rd party fab wording

John Lauer ·33b6fc3968 ·20d ago ·parent 05895ac

14 files changed +32−36

README.md+7−8 SKILL.md+1−2 fusion/adom-instapcb-2L.dru+1−1 fusion/adom-instapcb-2L.edru+3−3 fusion/adom-instapcb-4L.dru+1−1 fusion/adom-instapcb-4L.edru+2−2 kicad/adom-instapcb-2L.board-setup.json+2−2 kicad/adom-instapcb-2L.kicad_dru+2−2 kicad/adom-instapcb-4L.board-setup.json+2−2 kicad/adom-instapcb-4L.kicad_dru+1−1 page.json−2 rules/index.json+4−4 rules/records/adom-instapcb.json+5−5 tools/generate.py+1−1

README.md+7−8

@@ -29,7 +29,7 @@ To add or fix a limit, edit the record and run `python3 tools/generate.py`.  ## Vendors -Adom InstaPCB (house baseline, first by design), JLCPCB, PCBWay, OSH Park,+3rd party fab (baseline, first by design), JLCPCB, PCBWay, OSH Park, Seeed Fusion, Eurocircuits, Aisler, Elecrow, Advanced Circuits (4PCB), Sierra Circuits, MacroFab, NextPCB, ALLPCB. @@ -45,8 +45,8 @@ read date. Generated from the records, do not edit by hand. <!-- TABLE:BEGIN --> | Vendor | Process | Layers | Min trace mm / mil | Min space mm / mil | Min drill mm / mil | Min via drill / pad mm | Annular ring via / pad mm | Cu to edge mm | Hole to hole mm | Source (read 2026-09-03) | |---|---|---|---|---|---|---|---|---|---|---|---|-| Adom InstaPCB | standard | 2 | 0.1 / 3.94 | 0.1 / 3.94 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru |-| Adom InstaPCB | standard | 4 | 0.09 / 3.54 | 0.09 / 3.54 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru |+| 3rd party fab | standard | 2 | 0.1 / 3.94 | 0.1 / 3.94 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru |+| 3rd party fab | standard | 4 | 0.09 / 3.54 | 0.09 / 3.54 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru | | JLCPCB | standard | 2 | 0.1 / 4.0 | 0.1 / 4.0 | 0.15 / 5.91 | 0.15 / 0.25 | 0.18 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities | | JLCPCB | standard | 4 | 0.09 / 3.5 | 0.09 / 3.5 | 0.15 / 5.91 | 0.15 / 0.25 | 0.15 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities | | JLCPCB | standard | 6 | 0.09 / 3.5 | 0.09 / 3.5 | 0.15 / 5.91 | 0.15 / 0.25 | 0.15 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities |@@ -141,7 +141,7 @@ Requested host ConfRoomROG was offline, so verification ran on AdomLapper   `.dru` (treats the name as a library.io lookup). The `.dru` files are   for classic EAGLE, not Fusion. - Fusion `drc load` on a live board: all six 2-layer and 4-layer files for-  Adom InstaPCB, JLCPCB and PCBWay loaded with success, zero dialogs and+  the 3rd party fab, JLCPCB and PCBWay loaded with success, zero dialogs and   empty `fusion_alerts`. Exporting the rules after loading pcbway-2L.edru   returned exactly the PCBWay 2-layer values from the record. - KiCad DRC with custom rules: `jlcpcb-2L.kicad_dru` enforced by KiCad 10@@ -151,8 +151,7 @@ Requested host ConfRoomROG was offline, so verification ran on AdomLapper  ## Provenance and maintenance -All records were read from vendor pages on 2026-09-03 except Adom InstaPCB,-whose house rules ship as bundled `.edru` files inside the adom/fusion-bridge-add-in (no public capabilities page was reachable on 2026-09-03;-https://instapcb.com did not load). Re-read a vendor page before changing+All records were read from vendor pages on 2026-09-03 except the 3rd party fab,+whose rules ship as bundled `.edru` files inside the adom/fusion-bridge+add-in (no public capabilities page was reachable on 2026-09-03). Re-read a vendor page before changing its numbers, and update the `dateRead`.

SKILL.md+1−2

@@ -1,7 +1,7 @@ --- name: pcb-design-rules public: true-description: "Canonical PCB fab design rules (DRC) for every popular vendor, one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru files, KiCad .kicad_dru custom rules plus board-setup constraints JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read. This is where Adom bridges load design rules from: fusion_set_design_rules {fab, layers, druPath?} consumes the files on this page. Trigger words: design rules, DRC, JLCPCB rules, load PCBWay rules, InstaPCB rules, drc load, fab capabilities, min trace width, min drill, annular ring, copper clearance, edru, kicad_dru, design rule files by fab."+description: "Canonical PCB fab design rules (DRC) for every popular vendor, one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru files, KiCad .kicad_dru custom rules plus board-setup constraints JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read. This is where Adom bridges load design rules from: fusion_set_design_rules {fab, layers, druPath?} consumes the files on this page. Trigger words: design rules, DRC, JLCPCB rules, load PCBWay rules, drc load, fab capabilities, min trace width, min drill, annular ring, copper clearance, edru, kicad_dru, design rule files by fab." ---  # pcb-design-rules@@ -39,7 +39,6 @@ The page.json `discovery_triggers` registry entry reads: - DRC - JLCPCB rules - load PCBWay rules-- InstaPCB rules - drc load - fab capabilities - min trace width

fusion/adom-instapcb-2L.dru+1−1

@@ -1,4 +1,4 @@-description[Adom InstaPCB 2-layer design rules (standard process) |  | Min trace width: 0.1 mm (3.94 mil) - 1 oz copper | Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.1 mm, pad 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Drill range: 0.15 mm to 6.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz |  | House baseline of the Adom InstaPCB fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer. |  | Sources: | - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru (read 2026-09-03)]+description[3rd party fab 2-layer design rules (standard process) |  | Min trace width: 0.1 mm (3.94 mil) - 1 oz copper | Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.1 mm, pad 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Drill range: 0.15 mm to 6.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz |  | Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer. |  | Sources: | - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru (read 2026-09-03)]  layerSetup = (1*16) mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm

fusion/adom-instapcb-2L.edru+3−3

@@ -1,7 +1,7 @@ <?xml version="1.0" encoding="utf-8"?> <!DOCTYPE designrules SYSTEM "eagle.dtd"> <eagle version="9.7.0">-<designrules name="adom-instapcb-2L.edru">+<designrules name="3rd-party-fab-2L.edru"> <classes> <class number="0" name="default"> </class>@@ -65,7 +65,7 @@ <param name="msDrill" value="0.15mm"/> <param name="dpMaxLengthDifference" value="10mm"/> <param name="dpGapFactor" value="2.5"/>-<description language="en">Adom InstaPCB 2-layer design rules (standard process)+<description language="en">3rd party fab 2-layer design rules (standard process)  Min trace width: 0.1 mm (3.94 mil) - 1 oz copper Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets@@ -78,7 +78,7 @@ Drill range: 0.15 mm to 6.3 mm Board thickness options: 1.6 mm Copper weight options: 1 oz -House baseline of the Adom InstaPCB fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.+Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.  Sources: - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru (read 2026-09-03)

fusion/adom-instapcb-4L.dru+1−1

@@ -1,4 +1,4 @@-description[Adom InstaPCB 4-layer design rules (standard process) |  | Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer | Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.1 mm, pad 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Drill range: 0.15 mm to 6.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz |  | BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias. |  | Sources: | - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru (read 2026-09-03)]+description[3rd party fab 4-layer design rules (standard process) |  | Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer | Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.1 mm, pad 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Drill range: 0.15 mm to 6.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz |  | BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias. |  | Sources: | - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru (read 2026-09-03)]  layerSetup = (1*2*15*16) mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm

fusion/adom-instapcb-4L.edru+2−2

@@ -1,7 +1,7 @@ <?xml version="1.0" encoding="utf-8"?> <!DOCTYPE designrules SYSTEM "eagle.dtd"> <eagle version="9.7.0">-<designrules name="adom-instapcb-4L.edru">+<designrules name="3rd-party-fab-4L.edru"> <classes> <class number="0" name="default"> </class>@@ -65,7 +65,7 @@ <param name="msDrill" value="0.15mm"/> <param name="dpMaxLengthDifference" value="10mm"/> <param name="dpGapFactor" value="2.5"/>-<description language="en">Adom InstaPCB 4-layer design rules (standard process)+<description language="en">3rd party fab 4-layer design rules (standard process)  Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs

kicad/adom-instapcb-2L.board-setup.json+2−2

@@ -1,5 +1,5 @@ {-  "vendor": "Adom InstaPCB",+  "vendor": "3rd party fab",   "process": "standard",   "layerCount": 2,   "boardSetupConstraints": {@@ -20,7 +20,7 @@     {       "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru",       "dateRead": "2026-09-03",-      "kind": "bundled-house-rule-file"+      "kind": "bundled-rule-file"     }   ] }

kicad/adom-instapcb-2L.kicad_dru+2−2

@@ -1,6 +1,6 @@ (version 1) -# Adom InstaPCB 2-layer design rules (standard process)+# 3rd party fab 2-layer design rules (standard process) #  # Min trace width: 0.1 mm (3.94 mil) - 1 oz copper # Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets@@ -13,7 +13,7 @@ # Board thickness options: 1.6 mm # Copper weight options: 1 oz # -# House baseline of the Adom InstaPCB fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.+# Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer. #  # Sources: # - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru (read 2026-09-03)

kicad/adom-instapcb-4L.board-setup.json+2−2

@@ -1,5 +1,5 @@ {-  "vendor": "Adom InstaPCB",+  "vendor": "3rd party fab",   "process": "standard",   "layerCount": 4,   "boardSetupConstraints": {@@ -20,7 +20,7 @@     {       "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru",       "dateRead": "2026-09-03",-      "kind": "bundled-house-rule-file"+      "kind": "bundled-rule-file"     }   ] }

kicad/adom-instapcb-4L.kicad_dru+1−1

@@ -1,6 +1,6 @@ (version 1) -# Adom InstaPCB 4-layer design rules (standard process)+# 3rd party fab 4-layer design rules (standard process) #  # Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer # Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs

page.json−2

@@ -21,7 +21,6 @@     "fabrication",     "jlcpcb",     "pcbway",-    "instapcb",     "fusion",     "kicad",     "altium",@@ -51,7 +50,6 @@     "DRC",     "JLCPCB rules",     "load PCBWay rules",-    "InstaPCB rules",     "drc load",     "fab capabilities",     "min trace width",

rules/index.json+4−4

@@ -3,7 +3,7 @@   "unitNote": "mm primary, mil secondary (1 mil = 0.0254 mm)",   "vendors": [     {-      "vendor": "Adom InstaPCB",+      "vendor": "3rd party fab",       "vendorSlug": "adom-instapcb",       "process": "standard",       "layerCount": 2,@@ -20,12 +20,12 @@         {           "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru",           "dateRead": "2026-09-03",-          "kind": "bundled-house-rule-file"+          "kind": "bundled-rule-file"         }       ]     },     {-      "vendor": "Adom InstaPCB",+      "vendor": "3rd party fab",       "vendorSlug": "adom-instapcb",       "process": "standard",       "layerCount": 4,@@ -42,7 +42,7 @@         {           "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru",           "dateRead": "2026-09-03",-          "kind": "bundled-house-rule-file"+          "kind": "bundled-rule-file"         }       ]     },

rules/records/adom-instapcb.json+5−5

@@ -1,7 +1,7 @@ {-  "vendor": "Adom InstaPCB",+  "vendor": "3rd party fab",   "vendorSlug": "adom-instapcb",-  "vendorUrl": "https://instapcb.com",+  "vendorUrl": null,   "records": [     {       "process": "standard",@@ -23,9 +23,9 @@       "surfaceFinishes": [],       "maxBoardSize": null,       "drillRange": {"minMm": 0.15, "maxMm": 6.3, "note": "holes with diameter >= 6.3 mm are CNC routed from a smaller drilled hole; min non-plated hole 0.50 mm"},-      "notes": "House baseline of the Adom InstaPCB fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.",+      "notes": "Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.",       "sources": [-        {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-house-rule-file"}+        {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-rule-file"}       ]     },     {@@ -50,7 +50,7 @@       "drillRange": {"minMm": 0.15, "maxMm": 6.3, "note": "holes with diameter >= 6.3 mm are CNC routed from a smaller drilled hole; min non-plated hole 0.50 mm"},       "notes": "BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias.",       "sources": [-        {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-house-rule-file"}+        {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-rule-file"}       ]     }   ]

tools/generate.py+1−1

@@ -491,7 +491,7 @@ def gen_table(records):     sep = "|---|---|---|---|---|---|---|---|---|---|---|---|"     rows = [header, sep]     order = {v: i for i, v in enumerate([-        "Adom InstaPCB", "JLCPCB", "PCBWay", "OSH Park", "Seeed Fusion",+        "3rd party fab", "JLCPCB", "PCBWay", "OSH Park", "Seeed Fusion",         "Eurocircuits", "Aisler", "Elecrow", "Advanced Circuits", "Sierra Circuits",         "MacroFab", "NextPCB", "ALLPCB",     ])}