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PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

pcbdesign-rulesdrcfabricationjlcpcbpcbwayfusionkicadaltiumedrukicad_dru
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Rename the 3rd party fab rule packs: adom-3rdpartyfab

John Lauer ·676909d90d ·12d ago ·parent 33b6fc3
14 files changed +725−20
README.md+2−2altium/adom-3rdpartyfab-2L.RUL+44altium/adom-3rdpartyfab-4L.RUL+44fusion/adom-3rdpartyfab-2L.dru+71fusion/adom-3rdpartyfab-2L.edru+143fusion/adom-3rdpartyfab-4L.dru+71fusion/adom-3rdpartyfab-4L.edru+143kicad/adom-3rdpartyfab-2L.board-setup.json+26kicad/adom-3rdpartyfab-2L.kicad_dru+40kicad/adom-3rdpartyfab-4L.board-setup.json+26kicad/adom-3rdpartyfab-4L.kicad_dru+40rules/index.json+16−16rules/records/adom-3rdpartyfab.json+57verification/log.md+2−2
README.md+2−2
@@ -45,8 +45,8 @@ read date. Generated from the records, do not edit by hand. <!-- TABLE:BEGIN --> | Vendor | Process | Layers | Min trace mm / mil | Min space mm / mil | Min drill mm / mil | Min via drill / pad mm | Annular ring via / pad mm | Cu to edge mm | Hole to hole mm | Source (read 2026-09-03) | |---|---|---|---|---|---|---|---|---|---|---|---|-| 3rd party fab | standard | 2 | 0.1 / 3.94 | 0.1 / 3.94 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru |-| 3rd party fab | standard | 4 | 0.09 / 3.54 | 0.09 / 3.54 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru |+| 3rd party fab | standard | 2 | 0.1 / 3.94 | 0.1 / 3.94 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-2-Layer.edru |+| 3rd party fab | standard | 4 | 0.09 / 3.54 | 0.09 / 3.54 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-4-Layer.edru | | JLCPCB | standard | 2 | 0.1 / 4.0 | 0.1 / 4.0 | 0.15 / 5.91 | 0.15 / 0.25 | 0.18 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities | | JLCPCB | standard | 4 | 0.09 / 3.5 | 0.09 / 3.5 | 0.15 / 5.91 | 0.15 / 0.25 | 0.15 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities | | JLCPCB | standard | 6 | 0.09 / 3.5 | 0.09 / 3.5 | 0.15 / 5.91 | 0.15 / 0.25 | 0.15 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities |
altium/adom-3rdpartyfab-2L.RULadded+44
@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1mm|PreferredWidth=0.2mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/adom-3rdpartyfab-4L.RULadded+44
@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.09mm|PreferredWidth=0.18mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.09mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
fusion/adom-3rdpartyfab-2L.druadded+71
@@ -0,0 +1,71 @@+description[3rd party fab 2-layer design rules (standard process) |  | Min trace width: 0.1 mm (3.94 mil) - 1 oz copper | Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.1 mm, pad 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Drill range: 0.15 mm to 6.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz |  | Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer. |  | Sources: | - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-2-Layer.edru (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.94mil+mdWirePad = 3.94mil+mdWireVia = 3.94mil+mdPadPad = 5.91mil+mdPadVia = 3.94mil+mdViaVia = 3.94mil+mdSmdPad = 3.94mil+mdSmdVia = 3.94mil+mdSmdSmd = 3.94mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 3.94mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/adom-3rdpartyfab-2L.edruadded+143
@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="3rd-party-fab-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="no" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1mm"/>+<param name="mdWirePad" value="0.1mm"/>+<param name="mdWireVia" value="0.1mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1mm"/>+<param name="mdViaVia" value="0.1mm"/>+<param name="mdSmdPad" value="0.1mm"/>+<param name="mdSmdVia" value="0.1mm"/>+<param name="mdSmdSmd" value="0.1mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.1mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">3rd party fab 2-layer design rules (standard process)++Min trace width: 0.1 mm (3.94 mil) - 1 oz copper+Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.1 mm, pad 0.18 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.2 mm+Drill range: 0.15 mm to 6.3 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz++Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.++Sources:+- adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-2-Layer.edru (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/adom-3rdpartyfab-4L.druadded+71
@@ -0,0 +1,71 @@+description[3rd party fab 4-layer design rules (standard process) |  | Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer | Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.1 mm, pad 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Drill range: 0.15 mm to 6.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz |  | BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias. |  | Sources: | - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-4-Layer.edru (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.54mil+mdWirePad = 3.54mil+mdWireVia = 3.54mil+mdPadPad = 5.91mil+mdPadVia = 3.54mil+mdViaVia = 3.54mil+mdSmdPad = 3.54mil+mdSmdVia = 3.54mil+mdSmdSmd = 3.54mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 3.54mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/adom-3rdpartyfab-4L.edruadded+143
@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="3rd-party-fab-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.09mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.09mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="no" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.09mm"/>+<param name="mdWirePad" value="0.09mm"/>+<param name="mdWireVia" value="0.09mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.09mm"/>+<param name="mdViaVia" value="0.09mm"/>+<param name="mdSmdPad" value="0.09mm"/>+<param name="mdSmdVia" value="0.09mm"/>+<param name="mdSmdSmd" value="0.09mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.09mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">3rd party fab 4-layer design rules (standard process)++Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer+Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.1 mm, pad 0.18 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.2 mm+Drill range: 0.15 mm to 6.3 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz++BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias.++Sources:+- adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-4-Layer.edru (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
kicad/adom-3rdpartyfab-2L.board-setup.jsonadded+26
@@ -0,0 +1,26 @@+{+  "vendor": "3rd party fab",+  "process": "standard",+  "layerCount": 2,+  "boardSetupConstraints": {+    "minTrackWidthMm": 0.1,+    "minClearanceMm": 0.1,+    "minViaDrillMm": 0.15,+    "minViaDiameterMm": 0.25,+    "minHoleMm": 0.15,+    "copperEdgeClearanceMm": 0.2,+    "holeToHoleMm": 0.2,+    "annularRingViaMm": 0.1,+    "annularRingPadMm": 0.18,+    "silkMinLineWidthMm": null,+    "maskExpansionMm": 0.038+  },+  "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+  "sources": [+    {+      "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-2-Layer.edru",+      "dateRead": "2026-09-03",+      "kind": "bundled-rule-file"+    }+  ]+}
kicad/adom-3rdpartyfab-2L.kicad_druadded+40
@@ -0,0 +1,40 @@+(version 1)++# 3rd party fab 2-layer design rules (standard process)+# +# Min trace width: 0.1 mm (3.94 mil) - 1 oz copper+# Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.1 mm, pad 0.18 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.2 mm+# Drill range: 0.15 mm to 6.3 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# +# Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.+# +# Sources:+# - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-2-Layer.edru (read 2026-09-03)++(rule "min-track-width"+  (constraint track_width (min 0.1mm))+  (layer "*.Cu")+  (condition "A.type == 'track'"))++(rule "min-clearance"+  (constraint clearance (min 0.1mm))+  (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+  (constraint hole (min 0.15mm))+  (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+  (constraint via_diameter (min 0.25mm))+  (condition "A.type == 'via'"))++(rule "min-edge-clearance"+  (constraint edge_clearance (min 0.2mm))+  (condition "A.type == 'track'"))
kicad/adom-3rdpartyfab-4L.board-setup.jsonadded+26
@@ -0,0 +1,26 @@+{+  "vendor": "3rd party fab",+  "process": "standard",+  "layerCount": 4,+  "boardSetupConstraints": {+    "minTrackWidthMm": 0.09,+    "minClearanceMm": 0.09,+    "minViaDrillMm": 0.15,+    "minViaDiameterMm": 0.25,+    "minHoleMm": 0.15,+    "copperEdgeClearanceMm": 0.2,+    "holeToHoleMm": 0.2,+    "annularRingViaMm": 0.1,+    "annularRingPadMm": 0.18,+    "silkMinLineWidthMm": null,+    "maskExpansionMm": 0.038+  },+  "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+  "sources": [+    {+      "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-4-Layer.edru",+      "dateRead": "2026-09-03",+      "kind": "bundled-rule-file"+    }+  ]+}
kicad/adom-3rdpartyfab-4L.kicad_druadded+40
@@ -0,0 +1,40 @@+(version 1)++# 3rd party fab 4-layer design rules (standard process)+# +# Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer+# Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.1 mm, pad 0.18 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.2 mm+# Drill range: 0.15 mm to 6.3 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# +# BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias.+# +# Sources:+# - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-4-Layer.edru (read 2026-09-03)++(rule "min-track-width"+  (constraint track_width (min 0.09mm))+  (layer "*.Cu")+  (condition "A.type == 'track'"))++(rule "min-clearance"+  (constraint clearance (min 0.09mm))+  (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+  (constraint hole (min 0.15mm))+  (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+  (constraint via_diameter (min 0.25mm))+  (condition "A.type == 'via'"))++(rule "min-edge-clearance"+  (constraint edge_clearance (min 0.2mm))+  (condition "A.type == 'track'"))
rules/index.json+16−16
@@ -4,21 +4,21 @@   "vendors": [     {       "vendor": "3rd party fab",-      "vendorSlug": "adom-instapcb",+      "vendorSlug": "adom-3rdpartyfab",       "process": "standard",       "layerCount": 2,       "filesGenerated": true,       "files": {-        "record": "rules/records/adom-instapcb.json",-        "fusionEdru": "fusion/adom-instapcb-2L.edru",-        "fusionDru": "fusion/adom-instapcb-2L.dru",-        "kicadDru": "kicad/adom-instapcb-2L.kicad_dru",-        "kicadBoardSetup": "kicad/adom-instapcb-2L.board-setup.json",-        "altiumRul": "altium/adom-instapcb-2L.RUL"+        "record": "rules/records/adom-3rdpartyfab.json",+        "fusionEdru": "fusion/adom-3rdpartyfab-2L.edru",+        "fusionDru": "fusion/adom-3rdpartyfab-2L.dru",+        "kicadDru": "kicad/adom-3rdpartyfab-2L.kicad_dru",+        "kicadBoardSetup": "kicad/adom-3rdpartyfab-2L.board-setup.json",+        "altiumRul": "altium/adom-3rdpartyfab-2L.RUL"       },       "sources": [         {-          "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru",+          "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-2-Layer.edru",           "dateRead": "2026-09-03",           "kind": "bundled-rule-file"         }@@ -26,21 +26,21 @@     },     {       "vendor": "3rd party fab",-      "vendorSlug": "adom-instapcb",+      "vendorSlug": "adom-3rdpartyfab",       "process": "standard",       "layerCount": 4,       "filesGenerated": true,       "files": {-        "record": "rules/records/adom-instapcb.json",-        "fusionEdru": "fusion/adom-instapcb-4L.edru",-        "fusionDru": "fusion/adom-instapcb-4L.dru",-        "kicadDru": "kicad/adom-instapcb-4L.kicad_dru",-        "kicadBoardSetup": "kicad/adom-instapcb-4L.board-setup.json",-        "altiumRul": "altium/adom-instapcb-4L.RUL"+        "record": "rules/records/adom-3rdpartyfab.json",+        "fusionEdru": "fusion/adom-3rdpartyfab-4L.edru",+        "fusionDru": "fusion/adom-3rdpartyfab-4L.dru",+        "kicadDru": "kicad/adom-3rdpartyfab-4L.kicad_dru",+        "kicadBoardSetup": "kicad/adom-3rdpartyfab-4L.board-setup.json",+        "altiumRul": "altium/adom-3rdpartyfab-4L.RUL"       },       "sources": [         {-          "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru",+          "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-4-Layer.edru",           "dateRead": "2026-09-03",           "kind": "bundled-rule-file"         }
rules/records/adom-3rdpartyfab.jsonadded+57
@@ -0,0 +1,57 @@+{+  "vendor": "3rd party fab",+  "vendorSlug": "adom-3rdpartyfab",+  "vendorUrl": null,+  "records": [+    {+      "process": "standard",+      "layerCount": 2,+      "minTraceWidth": {"mm": 0.10, "mil": 3.94, "condition": "1 oz copper"},+      "minSpacing": {"mm": 0.10, "mil": 3.94, "condition": "1 oz copper, different nets"},+      "minDrill": {"mm": 0.15, "mil": 5.91},+      "minVia": {"drillMm": 0.15, "drillMil": 5.91, "padMm": 0.25, "padMil": 9.84},+      "annularRing": {"viaMm": 0.10, "viaMil": 3.94, "padMm": 0.18, "padMil": 7.09, "note": "0.25 mm or above preferred"},+      "copperToBoardEdge": {"mm": 0.20, "mil": 7.87},+      "holeToHole": {"mm": 0.20, "mil": 7.87},+      "maskExpansion": {"mm": 0.038, "mil": 1.50},+      "maskSliver": null,+      "silkLineWidth": null,+      "silkToCopper": null,+      "minCopperClearance": {"mm": 0.10, "mil": 3.94, "condition": "different nets"},+      "boardThicknessOptionsMm": [1.6],+      "copperWeightOptionsOz": [1],+      "surfaceFinishes": [],+      "maxBoardSize": null,+      "drillRange": {"minMm": 0.15, "maxMm": 6.3, "note": "holes with diameter >= 6.3 mm are CNC routed from a smaller drilled hole; min non-plated hole 0.50 mm"},+      "notes": "Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.",+      "sources": [+        {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-2-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-rule-file"}+      ]+    },+    {+      "process": "standard",+      "layerCount": 4,+      "minTraceWidth": {"mm": 0.09, "mil": 3.54, "condition": "1 oz copper, multilayer"},+      "minSpacing": {"mm": 0.09, "mil": 3.54, "condition": "1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs"},+      "minDrill": {"mm": 0.15, "mil": 5.91},+      "minVia": {"drillMm": 0.15, "drillMil": 5.91, "padMm": 0.25, "padMil": 9.84},+      "annularRing": {"viaMm": 0.10, "viaMil": 3.94, "padMm": 0.18, "padMil": 7.09, "note": "0.25 mm or above preferred"},+      "copperToBoardEdge": {"mm": 0.20, "mil": 7.87},+      "holeToHole": {"mm": 0.20, "mil": 7.87},+      "maskExpansion": {"mm": 0.038, "mil": 1.50},+      "maskSliver": null,+      "silkLineWidth": null,+      "silkToCopper": null,+      "minCopperClearance": {"mm": 0.09, "mil": 3.54, "condition": "different nets"},+      "boardThicknessOptionsMm": [1.6],+      "copperWeightOptionsOz": [1],+      "surfaceFinishes": [],+      "maxBoardSize": null,+      "drillRange": {"minMm": 0.15, "maxMm": 6.3, "note": "holes with diameter >= 6.3 mm are CNC routed from a smaller drilled hole; min non-plated hole 0.50 mm"},+      "notes": "BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias.",+      "sources": [+        {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-3rdPartyFab-4-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-rule-file"}+      ]+    }+  ]+}
verification/log.md+2−2
@@ -22,8 +22,8 @@ the bundled `fusion_load_design_rules` uses internally).  | File | drc load result | fusion_alerts | |---|---|---|-| adom-instapcb-2L.edru | success | 0 |-| adom-instapcb-4L.edru | success | 0 |+| adom-3rdpartyfab-2L.edru | success | 0 |+| adom-3rdpartyfab-4L.edru | success | 0 | | jlcpcb-2L.edru | success | 0 | | jlcpcb-4L.edru | success | 0 | | pcbway-2L.edru | success | 0 |