skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
← Commit history
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read from official capabilities pages on 2026-09-03, Adom InstaPCB house baseline from bundled seed .edru files. Generated Fusion .edru/.dru, KiCad .kicad_dru + board-setup JSON, Altium .RUL, comparison table, SKILL.md with discovery_triggers.
278 files changed
+21264−6
diff truncated
README.md+141−2SKILL.md+61altium/adom-instapcb-2L.RUL+44altium/adom-instapcb-4L.RUL+44altium/advanced-circuits-4pcb-2L.RUL+23altium/advanced-circuits-4pcb-4L.RUL+23altium/advanced-circuits-4pcb-advanced-2L.RUL+44altium/advanced-circuits-4pcb-advanced-4L.RUL+44altium/advanced-circuits-4pcb-advanced-standard-2L.RUL+44altium/advanced-circuits-4pcb-advanced-standard-4L.RUL+44altium/aisler-enig-2L.RUL+44altium/aisler-enig-4L.RUL+44altium/aisler-hasl-2L.RUL+44altium/allpcb-2L.RUL+44altium/allpcb-advanced-2L.RUL+44altium/allpcb-advanced-4L.RUL+44altium/allpcb-advanced-6L.RUL+44altium/elecrow-2L.RUL+23altium/elecrow-4L.RUL+23altium/elecrow-6L.RUL+23altium/eurocircuits-2L.RUL+44altium/eurocircuits-4L.RUL+44altium/eurocircuits-6L.RUL+44altium/eurocircuits-proto-2L.RUL+44altium/eurocircuits-proto-4L.RUL+44altium/jlcpcb-2L.RUL+44altium/jlcpcb-4L.RUL+44altium/jlcpcb-6L.RUL+44altium/macrofab-2L.RUL+23altium/macrofab-4L.RUL+23altium/macrofab-extended-2L.RUL+44altium/macrofab-extended-4L.RUL+44altium/nextpcb-2L.RUL+44altium/nextpcb-4L.RUL+44altium/nextpcb-6L.RUL+44altium/nextpcb-advanced-2L.RUL+23altium/osh-park-2L.RUL+44altium/osh-park-2oz-0.8mm-2L.RUL+44altium/osh-park-4L.RUL+44altium/osh-park-6L.RUL+44altium/osh-park-after-dark-2L.RUL+44altium/osh-park-flex-2L.RUL+44altium/pcbway-2L.RUL+44altium/pcbway-4L.RUL+44altium/pcbway-6L.RUL+44altium/pcbway-advanced-2L.RUL+44altium/pcbway-advanced-4L.RUL+44altium/pcbway-advanced-6L.RUL+44altium/seeed-fusion-2L.RUL+44altium/seeed-fusion-4L.RUL+44altium/seeed-fusion-6L.RUL+44altium/seeed-fusion-advanced-2L.RUL+37altium/seeed-fusion-advanced-4L.RUL+37altium/sierra-circuits-2L.RUL+44altium/sierra-circuits-4L.RUL+44fusion/adom-instapcb-2L.dru+71fusion/adom-instapcb-2L.edru+143fusion/adom-instapcb-4L.dru+71fusion/adom-instapcb-4L.edru+143fusion/advanced-circuits-4pcb-2L.dru+71fusion/advanced-circuits-4pcb-2L.edru+141fusion/advanced-circuits-4pcb-4L.dru+71fusion/advanced-circuits-4pcb-4L.edru+141fusion/advanced-circuits-4pcb-advanced-2L.dru+71fusion/advanced-circuits-4pcb-advanced-2L.edru+142fusion/advanced-circuits-4pcb-advanced-4L.dru+71fusion/advanced-circuits-4pcb-advanced-4L.edru+142fusion/advanced-circuits-4pcb-advanced-standard-2L.dru+71fusion/advanced-circuits-4pcb-advanced-standard-2L.edru+142fusion/advanced-circuits-4pcb-advanced-standard-4L.dru+71fusion/advanced-circuits-4pcb-advanced-standard-4L.edru+142fusion/aisler-enig-2L.dru+71fusion/aisler-enig-2L.edru+144fusion/aisler-enig-4L.dru+71fusion/aisler-enig-4L.edru+144fusion/aisler-hasl-2L.dru+71fusion/aisler-hasl-2L.edru+144fusion/allpcb-2L.dru+71fusion/allpcb-2L.edru+144fusion/allpcb-advanced-2L.dru+71fusion/allpcb-advanced-2L.edru+143fusion/allpcb-advanced-4L.dru+71fusion/allpcb-advanced-4L.edru+143fusion/allpcb-advanced-6L.dru+71fusion/allpcb-advanced-6L.edru+143fusion/elecrow-2L.dru+71fusion/elecrow-2L.edru+141fusion/elecrow-4L.dru+71fusion/elecrow-4L.edru+141fusion/elecrow-6L.dru+71fusion/elecrow-6L.edru+141fusion/eurocircuits-2L.dru+71fusion/eurocircuits-2L.edru+146fusion/eurocircuits-4L.dru+71fusion/eurocircuits-4L.edru+145fusion/eurocircuits-6L.dru+71fusion/eurocircuits-6L.edru+144fusion/eurocircuits-proto-2L.dru+71fusion/eurocircuits-proto-2L.edru+150fusion/eurocircuits-proto-4L.dru+71fusion/eurocircuits-proto-4L.edru+145fusion/jlcpcb-2L.dru+71fusion/jlcpcb-2L.edru+144fusion/jlcpcb-4L.dru+71fusion/jlcpcb-4L.edru+144fusion/jlcpcb-6L.dru+71fusion/jlcpcb-6L.edru+144fusion/macrofab-2L.dru+71fusion/macrofab-2L.edru+142fusion/macrofab-4L.dru+71fusion/macrofab-4L.edru+141fusion/macrofab-extended-2L.dru+71fusion/macrofab-extended-2L.edru+145fusion/macrofab-extended-4L.dru+71fusion/macrofab-extended-4L.edru+145fusion/nextpcb-2L.dru+71fusion/nextpcb-2L.edru+143fusion/nextpcb-4L.dru+71fusion/nextpcb-4L.edru+143fusion/nextpcb-6L.dru+71fusion/nextpcb-6L.edru+143fusion/nextpcb-advanced-2L.dru+71fusion/nextpcb-advanced-2L.edru+139fusion/osh-park-2L.dru+71fusion/osh-park-2L.edru+145fusion/osh-park-2oz-0.8mm-2L.dru+71fusion/osh-park-2oz-0.8mm-2L.edru+144fusion/osh-park-4L.dru+71fusion/osh-park-4L.edru+145fusion/osh-park-6L.dru+71fusion/osh-park-6L.edru+144fusion/osh-park-after-dark-2L.dru+71fusion/osh-park-after-dark-2L.edru+144fusion/osh-park-flex-2L.dru+71fusion/osh-park-flex-2L.edru+144fusion/pcbway-2L.dru+71fusion/pcbway-2L.edru+145fusion/pcbway-4L.dru+71fusion/pcbway-4L.edru+144fusion/pcbway-6L.dru+71fusion/pcbway-6L.edru+144fusion/pcbway-advanced-2L.dru+71fusion/pcbway-advanced-2L.edru+145fusion/pcbway-advanced-4L.dru+71fusion/pcbway-advanced-4L.edru+145fusion/pcbway-advanced-6L.dru+71fusion/pcbway-advanced-6L.edru+145fusion/seeed-fusion-2L.dru+71fusion/seeed-fusion-2L.edru+145fusion/seeed-fusion-4L.dru+71fusion/seeed-fusion-4L.edru+144fusion/seeed-fusion-6L.dru+71fusion/seeed-fusion-6L.edru+144fusion/seeed-fusion-advanced-2L.dru+71fusion/seeed-fusion-advanced-2L.edru+142fusion/seeed-fusion-advanced-4L.dru+71fusion/seeed-fusion-advanced-4L.edru+142fusion/sierra-circuits-2L.dru+71fusion/sierra-circuits-2L.edru+143fusion/sierra-circuits-4L.dru+71fusion/sierra-circuits-4L.edru+143kicad/adom-instapcb-2L.board-setup.json+26kicad/adom-instapcb-2L.kicad_dru+40kicad/adom-instapcb-4L.board-setup.json+26kicad/adom-instapcb-4L.kicad_dru+40kicad/advanced-circuits-4pcb-2L.board-setup.json+25kicad/advanced-circuits-4pcb-2L.kicad_dru+30kicad/advanced-circuits-4pcb-4L.board-setup.json+25kicad/advanced-circuits-4pcb-4L.kicad_dru+30kicad/advanced-circuits-4pcb-advanced-2L.board-setup.json+25kicad/advanced-circuits-4pcb-advanced-2L.kicad_dru+44kicad/advanced-circuits-4pcb-advanced-4L.board-setup.json+25kicad/advanced-circuits-4pcb-advanced-4L.kicad_dru+44kicad/advanced-circuits-4pcb-advanced-standard-2L.board-setup.json+25kicad/advanced-circuits-4pcb-advanced-standard-2L.kicad_dru+44kicad/advanced-circuits-4pcb-advanced-standard-4L.board-setup.json+25kicad/advanced-circuits-4pcb-advanced-standard-4L.kicad_dru+44kicad/aisler-enig-2L.board-setup.json+25kicad/aisler-enig-2L.kicad_dru+46kicad/aisler-enig-4L.board-setup.json+25kicad/aisler-enig-4L.kicad_dru+46kicad/aisler-hasl-2L.board-setup.json+25kicad/aisler-hasl-2L.kicad_dru+46kicad/allpcb-2L.board-setup.json+25kicad/allpcb-2L.kicad_dru+46kicad/allpcb-advanced-2L.board-setup.json+25kicad/allpcb-advanced-2L.kicad_dru+45kicad/allpcb-advanced-4L.board-setup.json+25kicad/allpcb-advanced-4L.kicad_dru+45kicad/allpcb-advanced-6L.board-setup.json+25kicad/allpcb-advanced-6L.kicad_dru+45kicad/elecrow-2L.board-setup.json+25kicad/elecrow-2L.kicad_dru+35kicad/elecrow-4L.board-setup.json+25kicad/elecrow-4L.kicad_dru+35kicad/elecrow-6L.board-setup.json+25kicad/elecrow-6L.kicad_dru+35kicad/eurocircuits-2L.board-setup.json+33kicad/eurocircuits-2L.kicad_dru+48kicad/eurocircuits-4L.board-setup.json+29kicad/eurocircuits-4L.kicad_dru+47kicad/eurocircuits-6L.board-setup.json+25kicad/eurocircuits-6L.kicad_dru+46kicad/eurocircuits-proto-2L.board-setup.json+49kicad/eurocircuits-proto-2L.kicad_dru+52kicad/eurocircuits-proto-4L.board-setup.json+29kicad/eurocircuits-proto-4L.kicad_dru+47kicad/jlcpcb-2L.board-setup.json+25kicad/jlcpcb-2L.kicad_dru+46kicad/jlcpcb-4L.board-setup.json+25kicad/jlcpcb-4L.kicad_dru+46kicad/jlcpcb-6L.board-setup.json+25kicad/jlcpcb-6L.kicad_dru+46kicad/macrofab-2L.board-setup.json+29kicad/macrofab-2L.kicad_dru+31kicad/macrofab-4L.board-setup.json+25kicad/macrofab-4L.kicad_dru+30kicad/macrofab-extended-2L.board-setup.json+29kicad/macrofab-extended-2L.kicad_dru+47kicad/macrofab-extended-4L.board-setup.json+29kicad/macrofab-extended-4L.kicad_dru+47kicad/nextpcb-2L.board-setup.json+25kicad/nextpcb-2L.kicad_dru+45kicad/nextpcb-4L.board-setup.json+25kicad/nextpcb-4L.kicad_dru+45kicad/nextpcb-6L.board-setup.json+25kicad/nextpcb-6L.kicad_dru+45kicad/nextpcb-advanced-2L.board-setup.json+25kicad/nextpcb-advanced-2L.kicad_dru+28kicad/osh-park-2L.board-setup.json+29kicad/osh-park-2L.kicad_dru+47kicad/osh-park-2oz-0.8mm-2L.board-setup.json+25kicad/osh-park-2oz-0.8mm-2L.kicad_dru+46kicad/osh-park-4L.board-setup.json+29kicad/osh-park-4L.kicad_dru+47kicad/osh-park-6L.board-setup.json+25kicad/osh-park-6L.kicad_dru+46kicad/osh-park-after-dark-2L.board-setup.json+25kicad/osh-park-after-dark-2L.kicad_dru+46kicad/osh-park-flex-2L.board-setup.json+25kicad/osh-park-flex-2L.kicad_dru+46kicad/pcbway-2L.board-setup.json+29kicad/pcbway-2L.kicad_dru+47kicad/pcbway-4L.board-setup.json+25kicad/pcbway-4L.kicad_dru+46kicad/pcbway-6L.board-setup.json+25kicad/pcbway-6L.kicad_dru+46kicad/pcbway-advanced-2L.board-setup.json+29kicad/pcbway-advanced-2L.kicad_dru+47kicad/pcbway-advanced-4L.board-setup.json+29kicad/pcbway-advanced-4L.kicad_dru+47kicad/pcbway-advanced-6L.board-setup.json+29kicad/pcbway-advanced-6L.kicad_dru+47kicad/seeed-fusion-2L.board-setup.json+29kicad/seeed-fusion-2L.kicad_dru+47kicad/seeed-fusion-4L.board-setup.json+25kicad/seeed-fusion-4L.kicad_dru+46kicad/seeed-fusion-6L.board-setup.json+25kicad/seeed-fusion-6L.kicad_dru+46kicad/seeed-fusion-advanced-2L.board-setup.json+25kicad/seeed-fusion-advanced-2L.kicad_dru+35kicad/seeed-fusion-advanced-4L.board-setup.json+25kicad/seeed-fusion-advanced-4L.kicad_dru+35kicad/sierra-circuits-2L.board-setup.json+25kicad/sierra-circuits-2L.kicad_dru+40kicad/sierra-circuits-4L.board-setup.json+25kicad/sierra-circuits-4L.kicad_dru+40page.json+43−4rules/index.json+1267rules/records/adom-instapcb.json+57rules/records/advanced-circuits-4pcb.json+528rules/records/aisler.json+262rules/records/allpcb.json+340rules/records/elecrow.json+208rules/records/eurocircuits.json+502rules/records/jlcpcb.json+290rules/records/macrofab.json+281rules/records/nextpcb.json+77README.md+141−2@@ -1,3 +1,142 @@-# PCB Design Rules+# PCB design rules by fab -Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.+The canonical home for PCB fabrication design rules (DRC limits) of every+popular vendor, in a form both humans and EDA bridges can consume.++One canonical JSON record per (vendor, process, layer count), generated into:++- `fusion/<slug>[-<process>]-<n>L.edru` and `.dru` for Autodesk Fusion 360+ electronics (EAGLE format, loads with the `drc load <path>` command)+- `kicad/<slug>[-<process>]-<n>L.kicad_dru` (KiCad custom rules) plus a+ `<same>.board-setup.json` with the Board Setup constraints+- `altium/<slug>[-<process>]-<n>L.RUL` (Altium design rules export, ASCII;+ not yet import-verified, see Verification)++Everything is generated by `tools/generate.py` from `rules/records/*.json`.+To add or fix a limit, edit the record and run `python3 tools/generate.py`.+`rules/index.json` maps every (vendor, process, layers) to its files.++## Rules of this page++- Source of truth is each vendor's own capabilities page. Every record's+ `sources` list names the URL and the date it was read. Nothing is copied+ from third-party blogs.+- Units: mm primary, mil secondary (1 mil = 0.0254 mm).+- Where a vendor publishes a range by condition (copper weight, process+ tier, partial-board BGA areas), the condition is recorded in the field's+ `condition` and in `notes`. Values are never averaged.+- `n/p` below means the vendor does not publish that limit.++## Vendors++Adom InstaPCB (house baseline, first by design), JLCPCB, PCBWay, OSH Park,+Seeed Fusion, Eurocircuits, Aisler, Elecrow, Advanced Circuits (4PCB),+Sierra Circuits, MacroFab, NextPCB, ALLPCB.++Per-vendor canonical records with full detail (mask, silk, board thickness+options, copper weights, surface finishes, max board size, notes, sources):+`rules/records/<vendor-slug>.json`.++## Comparison table++All numbers mm / mil as published on the vendor's capabilities page on the+read date. Generated from the records, do not edit by hand.++<!-- TABLE:BEGIN -->+| Vendor | Process | Layers | Min trace mm / mil | Min space mm / mil | Min drill mm / mil | Min via drill / pad mm | Annular ring via / pad mm | Cu to edge mm | Hole to hole mm | Source (read 2026-09-03) |+|---|---|---|---|---|---|---|---|---|---|---|---|+| Adom InstaPCB | standard | 2 | 0.1 / 3.94 | 0.1 / 3.94 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru |+| Adom InstaPCB | standard | 4 | 0.09 / 3.54 | 0.09 / 3.54 | 0.15 / 5.91 | 0.15 / 0.25 | 0.1 / 0.18 | 0.2 | 0.2 | adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru |+| JLCPCB | standard | 2 | 0.1 / 4.0 | 0.1 / 4.0 | 0.15 / 5.91 | 0.15 / 0.25 | 0.18 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities |+| JLCPCB | standard | 4 | 0.09 / 3.5 | 0.09 / 3.5 | 0.15 / 5.91 | 0.15 / 0.25 | 0.15 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities |+| JLCPCB | standard | 6 | 0.09 / 3.5 | 0.09 / 3.5 | 0.15 / 5.91 | 0.15 / 0.25 | 0.15 / n/p | 0.2 | 0.2 | https://jlcpcb.com/capabilities/pcb-capabilities |+| PCBWay | advanced | 2 | 0.0508 / 2.0 | 0.0508 / 2.0 | 0.15 / 5.91 | 0.15 / 0.3024 | 0.0762 / n/p | 0.2 | 0.3556 | https://www.pcbway.com/advanced-pcb-capabilities.html |+| PCBWay | advanced | 4 | 0.0508 / 2.0 | 0.0508 / 2.0 | 0.15 / 5.91 | 0.15 / 0.3024 | 0.0762 / n/p | 0.2 | 0.3556 | https://www.pcbway.com/advanced-pcb-capabilities.html |+| PCBWay | advanced | 6 | 0.0508 / 2.0 | 0.0508 / 2.0 | 0.15 / 5.91 | 0.15 / 0.3024 | 0.0762 / n/p | 0.2 | 0.3556 | https://www.pcbway.com/advanced-pcb-capabilities.html |+| PCBWay | standard | 2 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.2 / 7.87 | 0.2 / 0.454 | 0.127 / n/p | 0.25 | 0.2794 | https://www.pcbway.com/capabilities.html |+| PCBWay | standard | 4 | 0.1016 / 4.0 | 0.127 / 5.0 | 0.2 / 7.87 | 0.2 / 0.454 | 0.127 / n/p | 0.25 | 0.2794 | https://www.pcbway.com/capabilities.html |+| PCBWay | standard | 6 | 0.1016 / 4.0 | 0.127 / 5.0 | 0.2 / 7.87 | 0.2 / 0.454 | 0.127 / n/p | 0.25 | 0.2794 | https://www.pcbway.com/capabilities.html |+| OSH Park | 2oz-0.8mm | 2 | 0.1524 / 6.0 | 0.1524 / 6.0 | 0.254 / 10.0 | 0.254 / 0.508 | 0.127 / n/p | 0.381 | 0.127 | https://docs.oshpark.com/services/two-layer-hhdc/ |+| OSH Park | after-dark | 2 | 0.1524 / 6.0 | 0.1524 / 6.0 | 0.254 / 10.0 | 0.254 / 0.508 | 0.127 / n/p | 0.381 | 0.127 | https://docs.oshpark.com/services/afterdark/ |+| OSH Park | flex | 2 | 0.1524 / 6.0 | 0.1524 / 6.0 | 0.254 / 10.0 | 0.254 / 0.508 | 0.127 / n/p | 0.1524 | 0.127 | https://docs.oshpark.com/services/flex/ |+| OSH Park | standard | 2 | 0.1524 / 6.0 | 0.1524 / 6.0 | 0.254 / 10.0 | 0.254 / 0.508 | 0.127 / n/p | 0.381 | 0.127 | https://docs.oshpark.com/services/two-layer/ |+| OSH Park | standard | 4 | 0.127 / 5.0 | 0.127 / 5.0 | 0.254 / 10.0 | 0.254 / 0.4572 | 0.1016 / n/p | 0.381 | 0.127 | https://docs.oshpark.com/services/four-layer/ |+| OSH Park | standard | 6 | 0.127 / 5.0 | 0.127 / 5.0 | 0.2032 / 8.0 | 0.2032 / 0.4064 | 0.1016 / n/p | 0.381 | 0.127 | https://docs.oshpark.com/services/ |+| Seeed Fusion | advanced | 2 | 0.127 / 5.0 | 0.127 / 5.0 | 0.1 / 3.94 | 0.1 / 0.3032 | 0.1016 / n/p | n/p | 0.2286 | https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification |+| Seeed Fusion | advanced | 4 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.1 / 3.94 | 0.1 / 0.3032 | 0.1016 / n/p | n/p | 0.2286 | https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification |+| Seeed Fusion | standard | 2 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.2 / 7.87 | 0.2 / 0.4 | 0.1 / n/p | 0.3 | 0.3 | https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification |+| Seeed Fusion | standard | 4 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.2 / 7.87 | 0.2 / 0.4 | 0.1 / n/p | 0.3 | 0.3 | https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification |+| Seeed Fusion | standard | 6 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.2 / 7.87 | 0.2 / 0.4 | 0.1 / n/p | 0.3 | 0.3 | https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification |+| Eurocircuits | proto | 2 | 0.15 / 5.91 | 0.15 / 5.91 | 0.25 / 9.84 | 0.25 / 0.6 | 0.125 / n/p | 0.25 | 0.25 | https://www.eurocircuits.com/services/pcb-proto/ |+| Eurocircuits | proto | 4 | 0.15 / 5.91 | 0.15 / 5.91 | 0.25 / 9.84 | 0.25 / 0.6 | 0.125 / n/p | 0.25 | 0.25 | https://www.eurocircuits.com/services/pcb-proto/ |+| Eurocircuits | standard | 2 | 0.1 / 3.94 | 0.1 / 3.94 | 0.1 / 3.94 | 0.1 / 0.4 | 0.125 / n/p | 0.25 | 0.25 | https://www.eurocircuits.com/services/standard-pool/ |+| Eurocircuits | standard | 4 | 0.1 / 3.94 | 0.1 / 3.94 | 0.1 / 3.94 | 0.1 / 0.4 | 0.125 / n/p | 0.25 | 0.25 | https://www.eurocircuits.com/services/standard-pool/ |+| Eurocircuits | standard | 6 | 0.1 / 3.94 | 0.1 / 3.94 | 0.1 / 3.94 | 0.1 / 0.4 | 0.125 / n/p | 0.25 | 0.25 | https://www.eurocircuits.com/services/standard-pool/ |+| Aisler | enig | 2 | 0.125 / 5.0 | 0.125 / 5.0 | 0.25 / 10.0 | 0.25 / 0.45 | 0.1 / n/p | 0.3 | 0.3 | https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732 |+| Aisler | enig | 4 | 0.125 / 5.0 | 0.125 / 5.0 | 0.25 / 10.0 | 0.25 / 0.45 | 0.1 / n/p | 0.3 | 0.3 | https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733 |+| Aisler | hasl | 2 | 0.2 / 8.0 | 0.15 / 6.0 | 0.3 / 12.0 | 0.3 / 0.7 | 0.2 / n/p | 0.3 | 0.3 | https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735 |+| Elecrow | standard | 2 | 0.1524 / 6.0 | 0.1524 / 6.0 | 0.3 / 11.81 | 0.3 / n/a | n/p | n/p | n/p | https://www.elecrow.com/pcb-manufacturing.html |+| Elecrow | standard | 4 | 0.1524 / 6.0 | 0.1524 / 6.0 | 0.3 / 11.81 | 0.3 / n/a | n/p | n/p | n/p | https://www.elecrow.com/pcb-manufacturing.html |+| Elecrow | standard | 6 | 0.1524 / 6.0 | 0.1524 / 6.0 | 0.3 / 11.81 | 0.3 / n/a | n/p | n/p | n/p | https://www.elecrow.com/pcb-manufacturing.html |+| Sierra Circuits | standard | 2 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.15 / 5.9 | 0.15 / 0.4547 | 0.0254 / n/p | 0.254 | n/p | https://www.protoexpress.com/products/rigid-pcb/ |+| Sierra Circuits | standard | 4 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.15 / 5.9 | 0.15 / 0.4547 | 0.0254 / n/p | 0.254 | n/p | https://www.protoexpress.com/products/rigid-pcb/ |+| Sierra Circuits | turnkey-pro | 2 | 0.1016 / 4.0 | 0.1016 / 4.0 | n/p | n/p | n/p | n/p | n/p | https://www.protoexpress.com/ |+| Sierra Circuits | turnkey-pro | 4 | 0.1016 / 4.0 | 0.1016 / 4.0 | n/p | n/p | n/p | n/p | n/p | https://www.protoexpress.com/ |+| MacroFab | extended | 2 | 0.0762 / 3.0 | 0.0762 / 3.0 | 0.1016 / 4.0 | 0.1016 / 0.254 | 0.0762 / n/p | 0.0762 | 0.1524 | https://www.macrofab.com/capabilities/ |+| MacroFab | extended | 4 | 0.0762 / 3.0 | 0.0762 / 3.0 | 0.1016 / 4.0 | 0.1016 / 0.254 | 0.0762 / n/p | 0.0762 | 0.1524 | https://www.macrofab.com/capabilities/ |+| MacroFab | standard | 2 | 0.127 / 5.0 | 0.127 / 5.0 | 0.3048 / 12.0 | 0.3048 / n/a | n/p | n/p | n/p | https://support.macrofab.com/s/article/pcb-specifications-and-drc |+| MacroFab | standard | 4 | 0.127 / 5.0 | 0.127 / 5.0 | 0.3048 / 12.0 | 0.3048 / n/a | n/p | n/p | n/p | https://support.macrofab.com/s/article/pcb-specifications-and-drc |+| NextPCB | advanced | 2 | 0.0635 / 2.5 | 0.0635 / 2.5 | 0.15 / 5.91 | 0.075 / n/a | n/p | n/p | n/p | https://www.nextpcb.com/advanced-pcb-manufacturing-capabilities |+| NextPCB | standard | 2 | 0.0635 / 2.5 | 0.0762 / 3.0 | 0.15 / 5.91 | 0.2 / 0.3278 | 0.0889 / n/p | 0.2 | 0.3048 | https://www.nextpcb.com/pcb-capabilities |+| NextPCB | standard | 4 | 0.0635 / 2.5 | 0.0762 / 3.0 | 0.15 / 5.91 | 0.2 / 0.3278 | 0.0889 / n/p | 0.2 | 0.3048 | https://www.nextpcb.com/pcb-capabilities |+| NextPCB | standard | 6 | 0.0635 / 2.5 | 0.0762 / 3.0 | 0.15 / 5.91 | 0.2 / 0.3278 | 0.0889 / n/p | 0.2 | 0.3048 | https://www.nextpcb.com/pcb-capabilities |+| ALLPCB | advanced | 2 | 0.076 / 3.0 | 0.076 / 3.0 | 0.15 / 5.91 | 0.2 / 0.5 | 0.18 / n/p | 0.3 | n/p | https://www.allpcb.com/advanced_pcb_manufacturing_capability.html |+| ALLPCB | advanced | 4 | 0.076 / 3.0 | 0.076 / 3.0 | 0.15 / 5.91 | 0.15 / 0.25 | 0.18 / n/p | 0.3 | n/p | https://www.allpcb.com/advanced_pcb_manufacturing_capability.html |+| ALLPCB | advanced | 6 | 0.076 / 3.0 | 0.076 / 3.0 | 0.15 / 5.91 | 0.15 / 0.25 | 0.18 / n/p | 0.3 | n/p | https://www.allpcb.com/advanced_pcb_manufacturing_capability.html |+| ALLPCB | standard | 2 | 0.1 / 3.94 | 0.1 / 3.94 | 0.2 / 7.87 | 0.2 / 0.506 | 0.153 / n/p | 0.3 | 0.2032 | https://www.allpcb.com/standard_pcb_manufacturing_capability.html |+| Advanced Circuits (4PCB) | advanced | 2 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.127 / 5.0 | 0.127 / 0.508 | 0.1905 / n/p | 0.2032 | 0.254 | https://www.4pcb.com/pcb-capabilities.html |+| Advanced Circuits (4PCB) | advanced | 4 | 0.1016 / 4.0 | 0.1016 / 4.0 | 0.127 / 5.0 | 0.127 / 0.508 | 0.1905 / n/p | 0.2032 | 0.254 | https://www.4pcb.com/pcb-capabilities.html |+| Advanced Circuits (4PCB) | advanced-standard | 2 | 0.1397 / 5.5 | 0.1397 / 5.5 | 0.1499 / 5.9 | 0.1499 / 0.5309 | 0.1905 / n/p | 0.254 | 0.3048 | https://www.4pcb.com/pcb-capabilities.html |+| Advanced Circuits (4PCB) | advanced-standard | 4 | 0.1397 / 5.5 | 0.1397 / 5.5 | 0.1499 / 5.9 | 0.1499 / 0.5309 | 0.1905 / n/p | 0.254 | 0.3048 | https://www.4pcb.com/pcb-capabilities.html |+| Advanced Circuits (4PCB) | development-npi | 2 | 0.0762 / 3.0 | 0.0762 / 3.0 | n/p | n/p | 0.1905 / n/p | 0.127 | 0.2032 | https://www.4pcb.com/pcb-capabilities.html |+| Advanced Circuits (4PCB) | standard | 2 | 0.127 / 5.0 | 0.127 / 5.0 | 0.254 / 10.0 | 0.254 / n/a | n/p | n/p | n/p | https://www.4pcb.com/laminate-material-vendors.html |+| Advanced Circuits (4PCB) | standard | 4 | 0.127 / 5.0 | 0.127 / 5.0 | 0.254 / 10.0 | 0.254 / n/a | n/p | n/p | n/p | https://www.4pcb.com/laminate-material-vendors.html |+<!-- TABLE:END -->++## Using the files++Fusion 360 (via the adom fusion bridge):++```+adom-bridge --target <desktop> send_files '{"filePaths": ["/path/to/jlcpcb-2L.edru"]}'+adom-bridge --target <desktop> fusion_electron_run '{"command": "drc load C:/Users/<user>/Downloads/jlcpcb-2L.edru"}'+adom-bridge --target <desktop> fusion_alerts '{}'+```++`fusion_set_design_rules {fab, layers, druPath?}` (proposed verb shape) is+tracked on adom/fusion-bridge; see the issue linked in Verification.++KiCad: copy the `.kicad_dru` next to your board as+`<projectname>.kicad_dru`, or import the `board-setup.json` values into+Board Setup, Constraints. `kicad-cli pcb drc` and the GUI DRC both enforce+custom rules.++Altium: import the `.RUL` with Rules, Import. The ASCII export is generated+but not yet verified against a live Altium import; treat the JSON record as+canonical until verified.++## Verification++See `verification/` for the dated log and screenshots.++- Fusion 2026 extension check: pending+- Fusion `drc load` on a live board: pending+- KiCad DRC with custom rules: pending++## Provenance and maintenance++All records were read from vendor pages on 2026-09-03 except Adom InstaPCB,+whose house rules ship as bundled `.edru` files inside the adom/fusion-bridge+add-in (no public capabilities page was reachable on 2026-09-03;+https://instapcb.com did not load). Re-read a vendor page before changing+its numbers, and update the `dateRead`.
SKILL.mdadded+61@@ -0,0 +1,61 @@+---+name: pcb-design-rules+public: true+description: "Canonical PCB fab design rules (DRC) for every popular vendor, one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru files, KiCad .kicad_dru custom rules plus board-setup constraints JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read. This is where Adom bridges load design rules from: fusion_set_design_rules {fab, layers, druPath?} consumes the files on this page. Trigger words: design rules, DRC, JLCPCB rules, load PCBWay rules, InstaPCB rules, drc load, fab capabilities, min trace width, min drill, annular ring, copper clearance, edru, kicad_dru, design rule files by fab."+---++# pcb-design-rules++Canonical per-vendor PCB fab design rules, for humans and for the Adom EDA+bridges (Fusion, KiCad, Altium).++## When an agent should use this page++Any of: the user asks about design rules, DRC limits, fab capabilities, a+vendor's minimum trace width, spacing, drill, via or annular ring; the user+wants to load a fab's rules into Fusion (`drc load`), KiCad (custom rules)+or Altium; a bridge needs the rule files for `fusion_set_design_rules+{fab, layers, druPath?}` or its KiCad and Altium equivalents.++## Layout++- `rules/records/<vendor-slug>.json`: canonical records, one per+ (process, layerCount). Units mm primary, mil secondary. Every value+ carries `sources` (URL plus dateRead) and conditions are never averaged.+- `rules/index.json`: machine map from (vendor, process, layers) to files.+- `fusion/`: `.edru` (Fusion XML, what `drc load` takes) and classic+ EAGLE `.dru` text, per vendor, process and layer count.+- `kicad/`: `.kicad_dru` custom rules plus `.board-setup.json` constraints.+- `altium/`: `.RUL` ASCII exports (generated, not yet import-verified).+- `tools/generate.py`: regenerates every file from the records.+- `verification/`: dated proof that the generated files load in real EDA+ tools, with screenshots.++## discovery_triggers++The page.json `discovery_triggers` registry entry reads:++- design rules+- DRC+- JLCPCB rules+- load PCBWay rules+- InstaPCB rules+- drc load+- fab capabilities+- min trace width+- min drill size+- annular ring+- edru+- kicad_dru++## How to answer with this page++1. Find the vendor record in `rules/records/` or `rules/index.json`.+2. Quote numbers with their condition (copper weight, process tier) and the+ source URL plus read date. Never quote a limit without its condition.+3. For "load rules into Fusion", send the `.edru` with `send_files` then+ `fusion_electron_run {"command": "drc load <path>"}` and confirm+ `fusion_alerts` is empty.+4. If a vendor or limit is missing, check the vendor's own capabilities+ page, add a record, run `python3 tools/generate.py`, commit and push.+ A rule change is a publish, not a bridge release.
altium/adom-instapcb-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1mm|PreferredWidth=0.2mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/adom-instapcb-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.09mm|PreferredWidth=0.18mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.09mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/advanced-circuits-4pcb-2L.RULadded+23@@ -0,0 +1,23 @@+[Design Rules]+RuleCount=3++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.127mm|PreferredWidth=0.254mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.254mm
altium/advanced-circuits-4pcb-4L.RULadded+23@@ -0,0 +1,23 @@+[Design Rules]+RuleCount=3++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.127mm|PreferredWidth=0.254mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.254mm
altium/advanced-circuits-4pcb-advanced-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.508mm|PreferredViaHoleWidth=0.127mm|MinViaWidth=0.508mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.127mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.127mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1905mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2032mm
altium/advanced-circuits-4pcb-advanced-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.508mm|PreferredViaHoleWidth=0.127mm|MinViaWidth=0.508mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.127mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.127mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1905mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2032mm
altium/advanced-circuits-4pcb-advanced-standard-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1397mm|PreferredWidth=0.2794mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1397mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.5309mm|PreferredViaHoleWidth=0.1499mm|MinViaWidth=0.5309mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1499mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1499mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1905mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.254mm
altium/advanced-circuits-4pcb-advanced-standard-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1397mm|PreferredWidth=0.2794mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1397mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.5309mm|PreferredViaHoleWidth=0.1499mm|MinViaWidth=0.5309mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1499mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1499mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1905mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.254mm
altium/aisler-enig-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.125mm|PreferredWidth=0.25mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.125mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.45mm|PreferredViaHoleWidth=0.25mm|MinViaWidth=0.45mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.25mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.25mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/aisler-enig-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.125mm|PreferredWidth=0.25mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.125mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.45mm|PreferredViaHoleWidth=0.25mm|MinViaWidth=0.45mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.25mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.25mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/aisler-hasl-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.2mm|PreferredWidth=0.4mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.15mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.7mm|PreferredViaHoleWidth=0.3mm|MinViaWidth=0.7mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.3mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.3mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.2mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/allpcb-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1mm|PreferredWidth=0.2mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.506mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.506mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.2mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.153mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/allpcb-advanced-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.076mm|PreferredWidth=0.152mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.076mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.5mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.5mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.18mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/allpcb-advanced-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.076mm|PreferredWidth=0.152mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.076mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.18mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/allpcb-advanced-6L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.076mm|PreferredWidth=0.152mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.076mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.18mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/elecrow-2L.RULadded+23@@ -0,0 +1,23 @@+[Design Rules]+RuleCount=3++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1524mm|PreferredWidth=0.3048mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1524mm++[Rule3]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.3mm
altium/elecrow-4L.RULadded+23@@ -0,0 +1,23 @@+[Design Rules]+RuleCount=3++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1524mm|PreferredWidth=0.3048mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1524mm++[Rule3]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.3mm
altium/elecrow-6L.RULadded+23@@ -0,0 +1,23 @@+[Design Rules]+RuleCount=3++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1524mm|PreferredWidth=0.3048mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1524mm++[Rule3]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.3mm
altium/eurocircuits-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1mm|PreferredWidth=0.2mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4mm|PreferredViaHoleWidth=0.1mm|MinViaWidth=0.4mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.125mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.25mm
altium/eurocircuits-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1mm|PreferredWidth=0.2mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4mm|PreferredViaHoleWidth=0.1mm|MinViaWidth=0.4mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.125mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.25mm
altium/eurocircuits-6L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1mm|PreferredWidth=0.2mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4mm|PreferredViaHoleWidth=0.1mm|MinViaWidth=0.4mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.125mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.25mm
altium/eurocircuits-proto-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.15mm|PreferredWidth=0.3mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.15mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.6mm|PreferredViaHoleWidth=0.25mm|MinViaWidth=0.6mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.25mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.25mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.125mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.25mm
altium/eurocircuits-proto-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.15mm|PreferredWidth=0.3mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.15mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.6mm|PreferredViaHoleWidth=0.25mm|MinViaWidth=0.6mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.25mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.25mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.125mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.25mm
altium/jlcpcb-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1mm|PreferredWidth=0.2mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.18mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/jlcpcb-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.09mm|PreferredWidth=0.18mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.09mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.15mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/jlcpcb-6L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.09mm|PreferredWidth=0.18mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.09mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.15mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/macrofab-2L.RULadded+23@@ -0,0 +1,23 @@+[Design Rules]+RuleCount=3++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.127mm|PreferredWidth=0.254mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.3048mm
altium/macrofab-4L.RULadded+23@@ -0,0 +1,23 @@+[Design Rules]+RuleCount=3++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.127mm|PreferredWidth=0.254mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.3048mm
altium/macrofab-extended-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0762mm|PreferredWidth=0.1524mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0762mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.254mm|PreferredViaHoleWidth=0.1016mm|MinViaWidth=0.254mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1016mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1016mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0762mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.0762mm
altium/macrofab-extended-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0762mm|PreferredWidth=0.1524mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0762mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.254mm|PreferredViaHoleWidth=0.1016mm|MinViaWidth=0.254mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1016mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1016mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0762mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.0762mm
altium/nextpcb-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0635mm|PreferredWidth=0.127mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0762mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.3278mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.3278mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0889mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/nextpcb-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0635mm|PreferredWidth=0.127mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0762mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.3278mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.3278mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0889mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/nextpcb-6L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0635mm|PreferredWidth=0.127mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0762mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.3278mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.3278mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0889mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/nextpcb-advanced-2L.RULadded+23@@ -0,0 +1,23 @@+[Design Rules]+RuleCount=3++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0635mm|PreferredWidth=0.127mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0635mm++[Rule3]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm
altium/osh-park-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1524mm|PreferredWidth=0.3048mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1524mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.508mm|PreferredViaHoleWidth=0.254mm|MinViaWidth=0.508mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.254mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.254mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.127mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.381mm
altium/osh-park-2oz-0.8mm-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1524mm|PreferredWidth=0.3048mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1524mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.508mm|PreferredViaHoleWidth=0.254mm|MinViaWidth=0.508mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.254mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.254mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.127mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.381mm
altium/osh-park-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.127mm|PreferredWidth=0.254mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4572mm|PreferredViaHoleWidth=0.254mm|MinViaWidth=0.4572mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.254mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.254mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1016mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.381mm
altium/osh-park-6L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.127mm|PreferredWidth=0.254mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4064mm|PreferredViaHoleWidth=0.2032mm|MinViaWidth=0.4064mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2032mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.2032mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1016mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.381mm
altium/osh-park-after-dark-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1524mm|PreferredWidth=0.3048mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1524mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.508mm|PreferredViaHoleWidth=0.254mm|MinViaWidth=0.508mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.254mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.254mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.127mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.381mm
altium/osh-park-flex-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1524mm|PreferredWidth=0.3048mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1524mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.508mm|PreferredViaHoleWidth=0.254mm|MinViaWidth=0.508mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.254mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.254mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.127mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.1524mm
altium/pcbway-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.454mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.454mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.2mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.127mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.25mm
altium/pcbway-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.454mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.454mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.2mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.127mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.25mm
altium/pcbway-6L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.454mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.454mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.2mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.127mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.25mm
altium/pcbway-advanced-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0508mm|PreferredWidth=0.1016mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0508mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.3024mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.3024mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0762mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/pcbway-advanced-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0508mm|PreferredWidth=0.1016mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0508mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.3024mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.3024mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0762mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/pcbway-advanced-6L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.0508mm|PreferredWidth=0.1016mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.0508mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.3024mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.3024mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0762mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.2mm
altium/seeed-fusion-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.4mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.2mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/seeed-fusion-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.4mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.2mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/seeed-fusion-6L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4mm|PreferredViaHoleWidth=0.2mm|MinViaWidth=0.4mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.2mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.3mm
altium/seeed-fusion-advanced-2L.RULadded+37@@ -0,0 +1,37 @@+[Design Rules]+RuleCount=5++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.127mm|PreferredWidth=0.254mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.127mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.3032mm|PreferredViaHoleWidth=0.1mm|MinViaWidth=0.3032mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1016mm
altium/seeed-fusion-advanced-4L.RULadded+37@@ -0,0 +1,37 @@+[Design Rules]+RuleCount=5++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.3032mm|PreferredViaHoleWidth=0.1mm|MinViaWidth=0.3032mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.1mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.1mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.1016mm
altium/sierra-circuits-2L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4547mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.4547mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0254mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.254mm
altium/sierra-circuits-4L.RULadded+44@@ -0,0 +1,44 @@+[Design Rules]+RuleCount=6++[Rule1]+RuleKind=Width+RuleName=MinTraceWidth+Scope1=All+Scope2=+Attribute=MinWidth=0.1016mm|PreferredWidth=0.2032mm|MaxWidth=25.4mm++[Rule2]+RuleKind=Clearance+RuleName=MinClearance+Scope1=All+Scope2=+Attribute=Clearance=0.1016mm++[Rule3]+RuleKind=RoutingViaStyle+RuleName=MinVia+Scope1=All+Scope2=+Attribute=PreferredViaWidth=0.4547mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.4547mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm++[Rule4]+RuleKind=HoleSize+RuleName=MinHole+Scope1=All+Scope2=+Attribute=HoleWidth=0.15mm++[Rule5]+RuleKind=AnnularRing+RuleName=MinAnnularRing+Scope1=All+Scope2=+Attribute=MinAnnularRing=0.0254mm++[Rule6]+RuleKind=BoardOutlineClearance+RuleName=CopperToBoardEdge+Scope1=All+Scope2=+Attribute=Clearance=0.254mm
fusion/adom-instapcb-2L.druadded+71@@ -0,0 +1,71 @@+description[Adom InstaPCB 2-layer design rules (standard process) | | Min trace width: 0.1 mm (3.94 mil) - 1 oz copper | Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.1 mm, pad 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Drill range: 0.15 mm to 6.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz | | House baseline of the Adom InstaPCB fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer. | | Sources: | - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.94mil+mdWirePad = 3.94mil+mdWireVia = 3.94mil+mdPadPad = 5.91mil+mdPadVia = 3.94mil+mdViaVia = 3.94mil+mdSmdPad = 3.94mil+mdSmdVia = 3.94mil+mdSmdSmd = 3.94mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 3.94mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/adom-instapcb-2L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="adom-instapcb-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1mm"/>+<param name="mdWirePad" value="0.1mm"/>+<param name="mdWireVia" value="0.1mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1mm"/>+<param name="mdViaVia" value="0.1mm"/>+<param name="mdSmdPad" value="0.1mm"/>+<param name="mdSmdVia" value="0.1mm"/>+<param name="mdSmdSmd" value="0.1mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.1mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Adom InstaPCB 2-layer design rules (standard process)++Min trace width: 0.1 mm (3.94 mil) - 1 oz copper+Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.1 mm, pad 0.18 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.2 mm+Drill range: 0.15 mm to 6.3 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz++House baseline of the Adom InstaPCB fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.++Sources:+- adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/adom-instapcb-4L.druadded+71@@ -0,0 +1,71 @@+description[Adom InstaPCB 4-layer design rules (standard process) | | Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer | Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.1 mm, pad 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Drill range: 0.15 mm to 6.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz | | BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias. | | Sources: | - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.54mil+mdWirePad = 3.54mil+mdWireVia = 3.54mil+mdPadPad = 5.91mil+mdPadVia = 3.54mil+mdViaVia = 3.54mil+mdSmdPad = 3.54mil+mdSmdVia = 3.54mil+mdSmdSmd = 3.54mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 3.54mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/adom-instapcb-4L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="adom-instapcb-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.09mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.09mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.09mm"/>+<param name="mdWirePad" value="0.09mm"/>+<param name="mdWireVia" value="0.09mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.09mm"/>+<param name="mdViaVia" value="0.09mm"/>+<param name="mdSmdPad" value="0.09mm"/>+<param name="mdSmdVia" value="0.09mm"/>+<param name="mdSmdSmd" value="0.09mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.09mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Adom InstaPCB 4-layer design rules (standard process)++Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer+Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.1 mm, pad 0.18 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.2 mm+Drill range: 0.15 mm to 6.3 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz++BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias.++Sources:+- adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/advanced-circuits-4pcb-2L.druadded+71@@ -0,0 +1,71 @@+description[Advanced Circuits (4PCB) 2-layer design rules (standard process) | | Min trace width: 0.127 mm (5.0 mil) - outer trace, standard spec | Min spacing: 0.127 mm (5.0 mil) - standard spec trace/space 5/5 mils | Min drill: 0.254 mm (10.0 mil) | Min via: 0.254 mm hole | Board thickness options: 0.7874 mm, 1.5748 mm, 2.3622 mm, 3.175 mm | Copper weight options: 1 oz, 2 oz | Surface finishes: Lead-Free HAL | Max board size: 406.4 x 558.8 mm | | Standard spec: FR-4, 0 to 12 layers, IPC Class 2, quantity 1 to 10000 plus, turn time same day to 5 day. Hole tolerance plus or minus 0.005 in (0.127 mm). Rout tolerance plus or minus 0.010 in (0.254 mm). Solder mask LPI green, legend white. Board thickness options 0.031, 0.062, 0.093, 0.125 in. Standard finish pricing assumes lead-free HAL; ENIG or immersion silver at no extra cost if HAL unavailable. Same spec applies to 2 and 4 layer; page does not differentiate by layer count below 12. | | Sources: | - https://www.4pcb.com/laminate-material-vendors.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 5.0mil+msDrill = 10.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/advanced-circuits-4pcb-2L.edruadded+141@@ -0,0 +1,141 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="advanced-circuits-4pcb-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.127mm" preferredvalue="0.381mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.127mm" preferredvalue="0.254mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.254mm" preferredvalue="0.508mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.254mm" preferredvalue="0.508mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.127mm"/>+<param name="msDrill" value="0.254mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Advanced Circuits (4PCB) 2-layer design rules (standard process)++Min trace width: 0.127 mm (5.0 mil) - outer trace, standard spec+Min spacing: 0.127 mm (5.0 mil) - standard spec trace/space 5/5 mils+Min drill: 0.254 mm (10.0 mil)+Min via: 0.254 mm hole+Board thickness options: 0.7874 mm, 1.5748 mm, 2.3622 mm, 3.175 mm+Copper weight options: 1 oz, 2 oz+Surface finishes: Lead-Free HAL+Max board size: 406.4 x 558.8 mm++Standard spec: FR-4, 0 to 12 layers, IPC Class 2, quantity 1 to 10000 plus, turn time same day to 5 day. Hole tolerance plus or minus 0.005 in (0.127 mm). Rout tolerance plus or minus 0.010 in (0.254 mm). Solder mask LPI green, legend white. Board thickness options 0.031, 0.062, 0.093, 0.125 in. Standard finish pricing assumes lead-free HAL; ENIG or immersion silver at no extra cost if HAL unavailable. Same spec applies to 2 and 4 layer; page does not differentiate by layer count below 12.++Sources:+- https://www.4pcb.com/laminate-material-vendors.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/advanced-circuits-4pcb-4L.druadded+71@@ -0,0 +1,71 @@+description[Advanced Circuits (4PCB) 4-layer design rules (standard process) | | Min trace width: 0.127 mm (5.0 mil) - outer trace, standard spec | Min spacing: 0.127 mm (5.0 mil) - standard spec trace/space 5/5 mils | Min drill: 0.254 mm (10.0 mil) | Min via: 0.254 mm hole | Board thickness options: 0.7874 mm, 1.5748 mm, 2.3622 mm, 3.175 mm | Copper weight options: 1 oz, 2 oz | Surface finishes: Lead-Free HAL | Max board size: 406.4 x 558.8 mm | | Same standard spec as 2 layer. Typical 4-layer stackup published at 0.020, 0.031, 0.062, 0.093, 0.125 in finished thickness with 1 oz copper, max board size 16 x 22 in for 0.031 to 0.093 in, 14 x 20 in (355.6 x 508 mm) at 0.125 in. | | Sources: | - https://www.4pcb.com/laminate-material-vendors.html (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 5.0mil+msDrill = 10.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/advanced-circuits-4pcb-4L.edruadded+141@@ -0,0 +1,141 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="advanced-circuits-4pcb-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.127mm" preferredvalue="0.381mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.127mm" preferredvalue="0.254mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.254mm" preferredvalue="0.508mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.254mm" preferredvalue="0.508mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.127mm"/>+<param name="msDrill" value="0.254mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Advanced Circuits (4PCB) 4-layer design rules (standard process)++Min trace width: 0.127 mm (5.0 mil) - outer trace, standard spec+Min spacing: 0.127 mm (5.0 mil) - standard spec trace/space 5/5 mils+Min drill: 0.254 mm (10.0 mil)+Min via: 0.254 mm hole+Board thickness options: 0.7874 mm, 1.5748 mm, 2.3622 mm, 3.175 mm+Copper weight options: 1 oz, 2 oz+Surface finishes: Lead-Free HAL+Max board size: 406.4 x 558.8 mm++Same standard spec as 2 layer. Typical 4-layer stackup published at 0.020, 0.031, 0.062, 0.093, 0.125 in finished thickness with 1 oz copper, max board size 16 x 22 in for 0.031 to 0.093 in, 14 x 20 in (355.6 x 508 mm) at 0.125 in.++Sources:+- https://www.4pcb.com/laminate-material-vendors.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/advanced-circuits-4pcb-advanced-2L.druadded+71@@ -0,0 +1,71 @@+description[Advanced Circuits (4PCB) 2-layer design rules (advanced process) | | Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz base, 0.0762 mm (3 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz; inner 1 oz: 0.0889 mm (3.5 mil) | Min spacing: 0.1016 mm (4.0 mil) - outer layer trace to trace, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz, 0.0635 mm (2.5 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz | Min drill: 0.127 mm (5.0 mil) | Min via: 0.127 mm hole / 0.508 mm pad | Annular ring: via 0.1905 mm | Copper to board edge: 0.2032 mm | Hole to hole: 0.254 mm | Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz | Max board size: 482.6 x 558.8 mm | | Santa Clara CA, Advanced tier. Max board size 19 x 22 in. Min board thickness 0.008 in (0.2032 mm). PTH tolerance plus or minus 0.002 in (0.0508 mm). Minimum pad 0.01 in (0.254 mm). Min outer layer trace for filled and plated over vias 0.004 in (0.1016 mm). Aspect ratio PTH 12:1. | | Sources: | - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 8.0mil+mdDrill = 10.0mil+msWidth = 4.0mil+msDrill = 5.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.5mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.5mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.5mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.5mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/advanced-circuits-4pcb-advanced-2L.edruadded+142@@ -0,0 +1,142 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="advanced-circuits-4pcb-advanced-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.127mm" preferredvalue="0.254mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.127mm" preferredvalue="0.254mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2032mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.254mm" preferredvalue="0.254mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.2032mm"/>+<param name="mdDrill" value="0.254mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.127mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Advanced Circuits (4PCB) 2-layer design rules (advanced process)++Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz base, 0.0762 mm (3 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz; inner 1 oz: 0.0889 mm (3.5 mil)+Min spacing: 0.1016 mm (4.0 mil) - outer layer trace to trace, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz, 0.0635 mm (2.5 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz+Min drill: 0.127 mm (5.0 mil)+Min via: 0.127 mm hole / 0.508 mm pad+Annular ring: via 0.1905 mm+Copper to board edge: 0.2032 mm+Hole to hole: 0.254 mm+Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+Max board size: 482.6 x 558.8 mm++Santa Clara CA, Advanced tier. Max board size 19 x 22 in. Min board thickness 0.008 in (0.2032 mm). PTH tolerance plus or minus 0.002 in (0.0508 mm). Minimum pad 0.01 in (0.254 mm). Min outer layer trace for filled and plated over vias 0.004 in (0.1016 mm). Aspect ratio PTH 12:1.++Sources:+- https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1905mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1905mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1905mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1905mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/advanced-circuits-4pcb-advanced-4L.druadded+71@@ -0,0 +1,71 @@+description[Advanced Circuits (4PCB) 4-layer design rules (advanced process) | | Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz Cu base; inner 1 oz: 0.0889 mm (3.5 mil) | Min spacing: 0.1016 mm (4.0 mil) - outer layer trace to trace, 1 oz Cu base; inner 1 oz: 0.1016 mm (4 mil) | Min drill: 0.127 mm (5.0 mil) | Min via: 0.127 mm hole / 0.508 mm pad | Annular ring: via 0.1905 mm | Copper to board edge: 0.2032 mm | Hole to hole: 0.254 mm | Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz | Max board size: 482.6 x 558.8 mm | | Same Advanced tier values as 2 layer for this facility. | | Sources: | - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 8.0mil+mdDrill = 10.0mil+msWidth = 4.0mil+msDrill = 5.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.5mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.5mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.5mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.5mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/advanced-circuits-4pcb-advanced-4L.edruadded+142@@ -0,0 +1,142 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="advanced-circuits-4pcb-advanced-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.127mm" preferredvalue="0.254mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.127mm" preferredvalue="0.254mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2032mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.254mm" preferredvalue="0.254mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.2032mm"/>+<param name="mdDrill" value="0.254mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.127mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Advanced Circuits (4PCB) 4-layer design rules (advanced process)++Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz Cu base; inner 1 oz: 0.0889 mm (3.5 mil)+Min spacing: 0.1016 mm (4.0 mil) - outer layer trace to trace, 1 oz Cu base; inner 1 oz: 0.1016 mm (4 mil)+Min drill: 0.127 mm (5.0 mil)+Min via: 0.127 mm hole / 0.508 mm pad+Annular ring: via 0.1905 mm+Copper to board edge: 0.2032 mm+Hole to hole: 0.254 mm+Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+Max board size: 482.6 x 558.8 mm++Same Advanced tier values as 2 layer for this facility.++Sources:+- https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1905mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1905mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1905mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1905mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/advanced-circuits-4pcb-advanced-standard-2L.druadded+71@@ -0,0 +1,71 @@+description[Advanced Circuits (4PCB) 2-layer design rules (advanced-standard process) | | Min trace width: 0.1397 mm (5.5 mil) - outer layer, 1 oz Cu base; other weights: 0.0762 mm (3 mil) at 1/4 and 3/8 oz base, 0.1143 mm (4.5 mil) at 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil) | Min spacing: 0.1397 mm (5.5 mil) - outer layer trace to trace, 1 oz Cu base; 0.0762 mm (3 mil) at 1/4, 3/8, 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil) | Min drill: 0.1499 mm (5.9 mil) | Min via: 0.1499 mm hole / 0.5309 mm pad | Annular ring: via 0.1905 mm | Copper to board edge: 0.254 mm | Hole to hole: 0.3048 mm | Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz | Max board size: 406.4 x 558.8 mm | | Capabilities table is per facility and per tier; this object is Santa Clara, CA, Standard column. Min board thickness 0.01 in (0.254 mm), max board thickness 0.25 in (6.35 mm). PTH tolerance plus or minus 0.003 in (0.0762 mm). Drill to copper for PTH 0.01 in (0.254 mm). Minimum pad 0.015 in (0.381 mm), minimum isolated pad 0.01 in (0.254 mm). Min copper sliver between antipads 0.005 in (0.127 mm). Aspect ratio plated through holes 10:1 for drilled greater than 0.020 in, 10:1 for 0.010 to 0.019 in. Other facilities differ, e.g. Maple Grove MN standard outer 1 oz trace width is 0.1016 mm (4 mil), smallest mech via 0.0043 in (0.1092 mm). | | Sources: | - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.5mil+mdWirePad = 5.5mil+mdWireVia = 5.5mil+mdPadPad = 5.91mil+mdPadVia = 5.5mil+mdViaVia = 5.5mil+mdSmdPad = 5.5mil+mdSmdVia = 5.5mil+mdSmdSmd = 5.5mil+mdCopperDimension = 10.0mil+mdDrill = 12.0mil+msWidth = 5.5mil+msDrill = 5.9mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.5mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.5mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.5mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.5mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/advanced-circuits-4pcb-advanced-standard-2L.edruadded+142@@ -0,0 +1,142 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="advanced-circuits-4pcb-advanced-standard-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1397mm" preferredvalue="0.4191mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1397mm" preferredvalue="0.2794mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1499mm" preferredvalue="0.2998mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1499mm" preferredvalue="0.2998mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1397mm" preferredvalue="0.2794mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1397mm" preferredvalue="0.2794mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1397mm" preferredvalue="0.2794mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.254mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3048mm" preferredvalue="0.3048mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1397mm"/>+<param name="mdWirePad" value="0.1397mm"/>+<param name="mdWireVia" value="0.1397mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1397mm"/>+<param name="mdViaVia" value="0.1397mm"/>+<param name="mdSmdPad" value="0.1397mm"/>+<param name="mdSmdVia" value="0.1397mm"/>+<param name="mdSmdSmd" value="0.1397mm"/>+<param name="mdCopperDimension" value="0.254mm"/>+<param name="mdDrill" value="0.3048mm"/>+<param name="msWidth" value="0.1397mm"/>+<param name="msDrill" value="0.1499mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Advanced Circuits (4PCB) 2-layer design rules (advanced-standard process)++Min trace width: 0.1397 mm (5.5 mil) - outer layer, 1 oz Cu base; other weights: 0.0762 mm (3 mil) at 1/4 and 3/8 oz base, 0.1143 mm (4.5 mil) at 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)+Min spacing: 0.1397 mm (5.5 mil) - outer layer trace to trace, 1 oz Cu base; 0.0762 mm (3 mil) at 1/4, 3/8, 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)+Min drill: 0.1499 mm (5.9 mil)+Min via: 0.1499 mm hole / 0.5309 mm pad+Annular ring: via 0.1905 mm+Copper to board edge: 0.254 mm+Hole to hole: 0.3048 mm+Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+Max board size: 406.4 x 558.8 mm++Capabilities table is per facility and per tier; this object is Santa Clara, CA, Standard column. Min board thickness 0.01 in (0.254 mm), max board thickness 0.25 in (6.35 mm). PTH tolerance plus or minus 0.003 in (0.0762 mm). Drill to copper for PTH 0.01 in (0.254 mm). Minimum pad 0.015 in (0.381 mm), minimum isolated pad 0.01 in (0.254 mm). Min copper sliver between antipads 0.005 in (0.127 mm). Aspect ratio plated through holes 10:1 for drilled greater than 0.020 in, 10:1 for 0.010 to 0.019 in. Other facilities differ, e.g. Maple Grove MN standard outer 1 oz trace width is 0.1016 mm (4 mil), smallest mech via 0.0043 in (0.1092 mm).++Sources:+- https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1905mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1905mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1905mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1905mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/advanced-circuits-4pcb-advanced-standard-4L.druadded+71@@ -0,0 +1,71 @@+description[Advanced Circuits (4PCB) 4-layer design rules (advanced-standard process) | | Min trace width: 0.1397 mm (5.5 mil) - outer layer, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil); inner 1/2 oz: 0.0889 mm (3.5 mil) | Min spacing: 0.1397 mm (5.5 mil) - outer layer trace to trace, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil) | Min drill: 0.1499 mm (5.9 mil) | Min via: 0.1499 mm hole / 0.5309 mm pad | Annular ring: via 0.1905 mm | Copper to board edge: 0.254 mm | Hole to hole: 0.3048 mm | Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz | Max board size: 406.4 x 558.8 mm | | Same capabilities table values as 2 layer; buried vias mechanical drill minimum 0.0059 in (0.1499 mm), blind vias mechanical 0.0059 in, laser drilled blind via minimum 0.004 in (0.1016 mm). | | Sources: | - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.5mil+mdWirePad = 5.5mil+mdWireVia = 5.5mil+mdPadPad = 5.91mil+mdPadVia = 5.5mil+mdViaVia = 5.5mil+mdSmdPad = 5.5mil+mdSmdVia = 5.5mil+mdSmdSmd = 5.5mil+mdCopperDimension = 10.0mil+mdDrill = 12.0mil+msWidth = 5.5mil+msDrill = 5.9mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.5mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.5mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.5mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.5mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/advanced-circuits-4pcb-advanced-standard-4L.edruadded+142@@ -0,0 +1,142 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="advanced-circuits-4pcb-advanced-standard-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1397mm" preferredvalue="0.4191mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1397mm" preferredvalue="0.2794mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1499mm" preferredvalue="0.2998mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1499mm" preferredvalue="0.2998mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1397mm" preferredvalue="0.2794mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1397mm" preferredvalue="0.2794mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1397mm" preferredvalue="0.2794mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1397mm" preferredvalue="0.2794mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.254mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3048mm" preferredvalue="0.3048mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1397mm"/>+<param name="mdWirePad" value="0.1397mm"/>+<param name="mdWireVia" value="0.1397mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1397mm"/>+<param name="mdViaVia" value="0.1397mm"/>+<param name="mdSmdPad" value="0.1397mm"/>+<param name="mdSmdVia" value="0.1397mm"/>+<param name="mdSmdSmd" value="0.1397mm"/>+<param name="mdCopperDimension" value="0.254mm"/>+<param name="mdDrill" value="0.3048mm"/>+<param name="msWidth" value="0.1397mm"/>+<param name="msDrill" value="0.1499mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Advanced Circuits (4PCB) 4-layer design rules (advanced-standard process)++Min trace width: 0.1397 mm (5.5 mil) - outer layer, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil); inner 1/2 oz: 0.0889 mm (3.5 mil)+Min spacing: 0.1397 mm (5.5 mil) - outer layer trace to trace, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil)+Min drill: 0.1499 mm (5.9 mil)+Min via: 0.1499 mm hole / 0.5309 mm pad+Annular ring: via 0.1905 mm+Copper to board edge: 0.254 mm+Hole to hole: 0.3048 mm+Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+Max board size: 406.4 x 558.8 mm++Same capabilities table values as 2 layer; buried vias mechanical drill minimum 0.0059 in (0.1499 mm), blind vias mechanical 0.0059 in, laser drilled blind via minimum 0.004 in (0.1016 mm).++Sources:+- https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1905mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1905mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1905mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1905mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/aisler-enig-2L.druadded+71@@ -0,0 +1,71 @@+description[Aisler 2-layer design rules (enig process) | | Min trace width: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish | Min spacing: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish | Min drill: 0.25 mm (10.0 mil) | Min via: 0.25 mm hole / 0.45 mm pad | Annular ring: via 0.1 mm | Copper to board edge: 0.3 mm | Hole to hole: 0.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz | Surface finishes: ENIG | Max board size: 500 x 500 mm | | Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Min SMD pad size 200um (8 mil). Copper to NPTH clearance 250um (10 mil), copper to NPTH slot clearance 300um (12 mil) for slots under and over 1.8mm. PTH drill range 0.5mm to 5.6mm, PTH annular ring 300um. Via drill range 0.25mm to 0.45mm, via annular ring 100um. NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm, PTH slot annular ring 300um. Min silkscreen text height 800um (32 mil). Max silkscreen coverage 25% per board side. Castellated edges supported free of charge. Green soldermask (Peters Elpemer AS 2467), buried, blind, micro, and tented vias not supported. Via pad diameter not published. | | Sources: | - https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732 (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.92mil+mdWirePad = 4.92mil+mdWireVia = 4.92mil+mdPadPad = 5.91mil+mdPadVia = 4.92mil+mdViaVia = 4.92mil+mdSmdPad = 4.92mil+mdSmdVia = 4.92mil+mdSmdSmd = 4.92mil+mdCopperDimension = 11.81mil+mdDrill = 11.81mil+msWidth = 4.92mil+msDrill = 9.84mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/aisler-enig-2L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="aisler-enig-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.125mm" preferredvalue="0.375mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.125mm" preferredvalue="0.25mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.25mm" preferredvalue="0.5mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.25mm" preferredvalue="0.5mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.125mm" preferredvalue="0.25mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.125mm" preferredvalue="0.25mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.125mm" preferredvalue="0.25mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.3mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.125mm"/>+<param name="mdWirePad" value="0.125mm"/>+<param name="mdWireVia" value="0.125mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.125mm"/>+<param name="mdViaVia" value="0.125mm"/>+<param name="mdSmdPad" value="0.125mm"/>+<param name="mdSmdVia" value="0.125mm"/>+<param name="mdSmdSmd" value="0.125mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.3mm"/>+<param name="msWidth" value="0.125mm"/>+<param name="msDrill" value="0.25mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Aisler 2-layer design rules (enig process)++Min trace width: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish+Min spacing: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish+Min drill: 0.25 mm (10.0 mil)+Min via: 0.25 mm hole / 0.45 mm pad+Annular ring: via 0.1 mm+Copper to board edge: 0.3 mm+Hole to hole: 0.3 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz+Surface finishes: ENIG+Max board size: 500 x 500 mm++Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Min SMD pad size 200um (8 mil). Copper to NPTH clearance 250um (10 mil), copper to NPTH slot clearance 300um (12 mil) for slots under and over 1.8mm. PTH drill range 0.5mm to 5.6mm, PTH annular ring 300um. Via drill range 0.25mm to 0.45mm, via annular ring 100um. NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm, PTH slot annular ring 300um. Min silkscreen text height 800um (32 mil). Max silkscreen coverage 25% per board side. Castellated edges supported free of charge. Green soldermask (Peters Elpemer AS 2467), buried, blind, micro, and tented vias not supported. Via pad diameter not published.++Sources:+- https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732 (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/aisler-enig-4L.druadded+71@@ -0,0 +1,71 @@+description[Aisler 4-layer design rules (enig process) | | Min trace width: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish | Min spacing: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish | Min drill: 0.25 mm (10.0 mil) | Min via: 0.25 mm hole / 0.45 mm pad | Annular ring: via 0.1 mm | Copper to board edge: 0.3 mm | Hole to hole: 0.3 mm | Board thickness options: 0.8 mm, 1.6 mm | Copper weight options: 1 oz | Surface finishes: ENIG | Max board size: 500 x 500 mm | | Source page states rules are valid for both 0.8mm and 1.6mm PCB thickness. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. PTH drill range 0.5mm to 5.6mm, via drill range 0.25mm to 0.45mm, via annular ring 100um, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges supported free of charge. Green soldermask. Via pad diameter not published. | | Sources: | - https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733 (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.92mil+mdWirePad = 4.92mil+mdWireVia = 4.92mil+mdPadPad = 5.91mil+mdPadVia = 4.92mil+mdViaVia = 4.92mil+mdSmdPad = 4.92mil+mdSmdVia = 4.92mil+mdSmdSmd = 4.92mil+mdCopperDimension = 11.81mil+mdDrill = 11.81mil+msWidth = 4.92mil+msDrill = 9.84mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/aisler-enig-4L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="aisler-enig-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.125mm" preferredvalue="0.375mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.125mm" preferredvalue="0.25mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.25mm" preferredvalue="0.5mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.25mm" preferredvalue="0.5mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.125mm" preferredvalue="0.25mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.125mm" preferredvalue="0.25mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.125mm" preferredvalue="0.25mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.125mm" preferredvalue="0.25mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.3mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.125mm"/>+<param name="mdWirePad" value="0.125mm"/>+<param name="mdWireVia" value="0.125mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.125mm"/>+<param name="mdViaVia" value="0.125mm"/>+<param name="mdSmdPad" value="0.125mm"/>+<param name="mdSmdVia" value="0.125mm"/>+<param name="mdSmdSmd" value="0.125mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.3mm"/>+<param name="msWidth" value="0.125mm"/>+<param name="msDrill" value="0.25mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Aisler 4-layer design rules (enig process)++Min trace width: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish+Min spacing: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish+Min drill: 0.25 mm (10.0 mil)+Min via: 0.25 mm hole / 0.45 mm pad+Annular ring: via 0.1 mm+Copper to board edge: 0.3 mm+Hole to hole: 0.3 mm+Board thickness options: 0.8 mm, 1.6 mm+Copper weight options: 1 oz+Surface finishes: ENIG+Max board size: 500 x 500 mm++Source page states rules are valid for both 0.8mm and 1.6mm PCB thickness. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. PTH drill range 0.5mm to 5.6mm, via drill range 0.25mm to 0.45mm, via annular ring 100um, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges supported free of charge. Green soldermask. Via pad diameter not published.++Sources:+- https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733 (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/aisler-hasl-2L.druadded+71@@ -0,0 +1,71 @@+description[Aisler 2-layer design rules (hasl process) | | Min trace width: 0.2 mm (8.0 mil) - Cu 35um (1oz), HASL finish | Min spacing: 0.15 mm (6.0 mil) - Cu 35um (1oz), HASL finish | Min drill: 0.3 mm (12.0 mil) | Min via: 0.3 mm hole / 0.7 mm pad | Annular ring: via 0.2 mm | Copper to board edge: 0.3 mm | Hole to hole: 0.3 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz | Surface finishes: HASL | Max board size: 500 x 500 mm | | Lead-free HASL. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Via drill range 0.3mm to 0.45mm, drill may be enlarged up to 0.45mm. PTH drill range 0.5mm to 5.6mm, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges not supported with HASL. Green soldermask (Peters Elpemer AS 2467). Via pad diameter not published. | | Sources: | - https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735 (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.91mil+mdWirePad = 5.91mil+mdWireVia = 5.91mil+mdPadPad = 5.91mil+mdPadVia = 5.91mil+mdViaVia = 5.91mil+mdSmdPad = 5.91mil+mdSmdVia = 5.91mil+mdSmdSmd = 5.91mil+mdCopperDimension = 11.81mil+mdDrill = 11.81mil+msWidth = 7.87mil+msDrill = 11.81mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.87mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.87mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.87mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.87mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/aisler-hasl-2L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="aisler-hasl-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.2mm" preferredvalue="0.6mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.2mm" preferredvalue="0.4mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.3mm" preferredvalue="0.6mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.3mm" preferredvalue="0.6mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.3mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.15mm"/>+<param name="mdWirePad" value="0.15mm"/>+<param name="mdWireVia" value="0.15mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.15mm"/>+<param name="mdViaVia" value="0.15mm"/>+<param name="mdSmdPad" value="0.15mm"/>+<param name="mdSmdVia" value="0.15mm"/>+<param name="mdSmdSmd" value="0.15mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.3mm"/>+<param name="msWidth" value="0.2mm"/>+<param name="msDrill" value="0.3mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Aisler 2-layer design rules (hasl process)++Min trace width: 0.2 mm (8.0 mil) - Cu 35um (1oz), HASL finish+Min spacing: 0.15 mm (6.0 mil) - Cu 35um (1oz), HASL finish+Min drill: 0.3 mm (12.0 mil)+Min via: 0.3 mm hole / 0.7 mm pad+Annular ring: via 0.2 mm+Copper to board edge: 0.3 mm+Hole to hole: 0.3 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz+Surface finishes: HASL+Max board size: 500 x 500 mm++Lead-free HASL. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Via drill range 0.3mm to 0.45mm, drill may be enlarged up to 0.45mm. PTH drill range 0.5mm to 5.6mm, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges not supported with HASL. Green soldermask (Peters Elpemer AS 2467). Via pad diameter not published.++Sources:+- https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735 (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.2mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.2mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.2mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.2mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/allpcb-2L.druadded+71@@ -0,0 +1,71 @@+description[ALLPCB 2-layer design rules (standard process) | | Min trace width: 0.1 mm (3.94 mil) - all copper weights; vendor suggests 6mil (0.15mm) or more to save cost | Min spacing: 0.1 mm (3.94 mil) - all copper weights; vendor suggests 6mil (0.15mm) or more to save cost | Min drill: 0.2 mm (7.87 mil) | Min via: 0.2 mm hole / 0.506 mm pad | Annular ring: via 0.153 mm | Copper to board edge: 0.3 mm | Hole to hole: 0.2032 mm | Board thickness options: 0.4 mm, 3.2 mm | Copper weight options: 0.5 oz, 1 oz, 2 oz | Surface finishes: HASL, Immersion Gold, Immersion Silver, Immersion Tin, OSP, Hard Gold plating, Soft Gold plating, NiPdAu | Max board size: 506 x 580 mm | | Single published limit set covers 1 to 14 layers, so this entry also applies to 4 and 6 layer boards. Board thickness is a continuous 0.4 to 3.2mm range. Copper: outer 1oz to 2oz (35 to 70um), inner 0.5oz to 2oz (18 to 70um). Min dimension 80x80mm. Drill range 0.2 to 6.5mm, finished CNC hole 0.2 to 6.5mm, hole size tolerance ±0.075mm. Copper to V-cut line 0.4mm (15.748mil) for panelized boards. Via space same net 8mil (0.2032mm), different nets 17mil (0.4318mm), component vias different nets 24mil (0.6096mm). Annular ring 6mil or larger where surrounded by traces. Min slot width 0.6mm, finished slot 0.45mm for HASL and 0.5mm for other finishes. Board thickness to via diameter ratio 6:1, 7:1 to 8:1 adds a fabrication day. Min character height 0.8mm (31.4961mil), width to height ratio 1:5. Mask sliver recorded from solder mask bridge value 0.1mm (price may rise). | | Sources: | - https://www.allpcb.com/standard_pcb_manufacturing_capability.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.94mil+mdWirePad = 3.94mil+mdWireVia = 3.94mil+mdPadPad = 5.91mil+mdPadVia = 3.94mil+mdViaVia = 3.94mil+mdSmdPad = 3.94mil+mdSmdVia = 3.94mil+mdSmdSmd = 3.94mil+mdCopperDimension = 11.81mil+mdDrill = 8.0mil+msWidth = 3.94mil+msDrill = 7.87mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 6.02mil+rlMaxViaOuter = 20mil+rlMinViaInner = 6.02mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 6.02mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 6.02mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/allpcb-2L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="allpcb-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.2mm" preferredvalue="0.4mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.2mm" preferredvalue="0.4mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2032mm" preferredvalue="0.2032mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1mm"/>+<param name="mdWirePad" value="0.1mm"/>+<param name="mdWireVia" value="0.1mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1mm"/>+<param name="mdViaVia" value="0.1mm"/>+<param name="mdSmdPad" value="0.1mm"/>+<param name="mdSmdVia" value="0.1mm"/>+<param name="mdSmdSmd" value="0.1mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.2032mm"/>+<param name="msWidth" value="0.1mm"/>+<param name="msDrill" value="0.2mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">ALLPCB 2-layer design rules (standard process)++Min trace width: 0.1 mm (3.94 mil) - all copper weights; vendor suggests 6mil (0.15mm) or more to save cost+Min spacing: 0.1 mm (3.94 mil) - all copper weights; vendor suggests 6mil (0.15mm) or more to save cost+Min drill: 0.2 mm (7.87 mil)+Min via: 0.2 mm hole / 0.506 mm pad+Annular ring: via 0.153 mm+Copper to board edge: 0.3 mm+Hole to hole: 0.2032 mm+Board thickness options: 0.4 mm, 3.2 mm+Copper weight options: 0.5 oz, 1 oz, 2 oz+Surface finishes: HASL, Immersion Gold, Immersion Silver, Immersion Tin, OSP, Hard Gold plating, Soft Gold plating, NiPdAu+Max board size: 506 x 580 mm++Single published limit set covers 1 to 14 layers, so this entry also applies to 4 and 6 layer boards. Board thickness is a continuous 0.4 to 3.2mm range. Copper: outer 1oz to 2oz (35 to 70um), inner 0.5oz to 2oz (18 to 70um). Min dimension 80x80mm. Drill range 0.2 to 6.5mm, finished CNC hole 0.2 to 6.5mm, hole size tolerance ±0.075mm. Copper to V-cut line 0.4mm (15.748mil) for panelized boards. Via space same net 8mil (0.2032mm), different nets 17mil (0.4318mm), component vias different nets 24mil (0.6096mm). Annular ring 6mil or larger where surrounded by traces. Min slot width 0.6mm, finished slot 0.45mm for HASL and 0.5mm for other finishes. Board thickness to via diameter ratio 6:1, 7:1 to 8:1 adds a fabrication day. Min character height 0.8mm (31.4961mil), width to height ratio 1:5. Mask sliver recorded from solder mask bridge value 0.1mm (price may rise).++Sources:+- https://www.allpcb.com/standard_pcb_manufacturing_capability.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.153mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.153mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.153mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.153mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/allpcb-advanced-2L.druadded+71@@ -0,0 +1,71 @@+description[ALLPCB 2-layer design rules (advanced process) | | Min trace width: 0.076 mm (3.0 mil) - 1oz copper | Min spacing: 0.076 mm (3.0 mil) - 1oz copper | Min drill: 0.15 mm (5.91 mil) | Min via: 0.2 mm hole / 0.5 mm pad | Annular ring: via 0.18 mm | Copper to board edge: 0.3 mm | Board thickness options: 0.4 mm, 4.0 mm | Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz | Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating | Max board size: 630 x 520 mm | | Double-side board via/pad: 0.2mm inner diameter, 0.5mm outer diameter; outer diameter must be 0.1mm larger than inner, 0.15mm preferred; preferred min via hole 0.2mm. Trace/spacing by copper weight: 1oz 0.076mm, 2oz 0.14mm (5.5118mil), 3oz 0.2mm (7.874mil), 4oz 0.25mm (9.8425mil), 5oz 0.35mm (13.7795mil), 6oz 0.45mm (17.7165mil). Trace width tolerance ±20%. Annular ring: plated DIP holes 1oz recommended 0.2mm, limit 0.18mm; non-plated DIP holes recommended 0.4mm (15.748mil). Min plated slot 0.7mm (27.5591mil), min non-plated slot 0.8mm (31.4961mil). Board thickness to min plated hole ratio 10:1. Plated half hole diameter 0.4mm or more, spacing 0.35mm (13.7795mil). Min single PCB size 10x5mm. Copper to board edge 0.3mm at non-stamp-hole panel areas; V-cut line to copper 0.4mm. Mask sliver recorded from min solder bridge width: green 0.075mm, other colors 0.125mm (4.9213mil). Silk text height 0.75mm (29.5276mil). BGA pad diameter 0.2mm or more. Edge rail 4mm or more. | | Sources: | - https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 2.99mil+mdWirePad = 2.99mil+mdWireVia = 2.99mil+mdPadPad = 5.91mil+mdPadVia = 2.99mil+mdViaVia = 2.99mil+mdSmdPad = 2.99mil+mdSmdVia = 2.99mil+mdSmdSmd = 2.99mil+mdCopperDimension = 11.81mil+mdDrill = 7.87mil+msWidth = 2.99mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.09mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.09mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.09mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.09mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/allpcb-advanced-2L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="allpcb-advanced-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.076mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.076mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.076mm"/>+<param name="mdWirePad" value="0.076mm"/>+<param name="mdWireVia" value="0.076mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.076mm"/>+<param name="mdViaVia" value="0.076mm"/>+<param name="mdSmdPad" value="0.076mm"/>+<param name="mdSmdVia" value="0.076mm"/>+<param name="mdSmdSmd" value="0.076mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.076mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">ALLPCB 2-layer design rules (advanced process)++Min trace width: 0.076 mm (3.0 mil) - 1oz copper+Min spacing: 0.076 mm (3.0 mil) - 1oz copper+Min drill: 0.15 mm (5.91 mil)+Min via: 0.2 mm hole / 0.5 mm pad+Annular ring: via 0.18 mm+Copper to board edge: 0.3 mm+Board thickness options: 0.4 mm, 4.0 mm+Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating+Max board size: 630 x 520 mm++Double-side board via/pad: 0.2mm inner diameter, 0.5mm outer diameter; outer diameter must be 0.1mm larger than inner, 0.15mm preferred; preferred min via hole 0.2mm. Trace/spacing by copper weight: 1oz 0.076mm, 2oz 0.14mm (5.5118mil), 3oz 0.2mm (7.874mil), 4oz 0.25mm (9.8425mil), 5oz 0.35mm (13.7795mil), 6oz 0.45mm (17.7165mil). Trace width tolerance ±20%. Annular ring: plated DIP holes 1oz recommended 0.2mm, limit 0.18mm; non-plated DIP holes recommended 0.4mm (15.748mil). Min plated slot 0.7mm (27.5591mil), min non-plated slot 0.8mm (31.4961mil). Board thickness to min plated hole ratio 10:1. Plated half hole diameter 0.4mm or more, spacing 0.35mm (13.7795mil). Min single PCB size 10x5mm. Copper to board edge 0.3mm at non-stamp-hole panel areas; V-cut line to copper 0.4mm. Mask sliver recorded from min solder bridge width: green 0.075mm, other colors 0.125mm (4.9213mil). Silk text height 0.75mm (29.5276mil). BGA pad diameter 0.2mm or more. Edge rail 4mm or more.++Sources:+- https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.18mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.18mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.18mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.18mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/allpcb-advanced-4L.druadded+71@@ -0,0 +1,71 @@+description[ALLPCB 4-layer design rules (advanced process) | | Min trace width: 0.076 mm (3.0 mil) - 1oz copper | Min spacing: 0.076 mm (3.0 mil) - 1oz copper | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.18 mm | Copper to board edge: 0.3 mm | Board thickness options: 0.4 mm, 4.0 mm | Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz | Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating | Max board size: 630 x 520 mm | | Multi-layer board via/pad: 0.15mm inner diameter, 0.25mm outer diameter. Other limits as 2 layer entry. | | Sources: | - https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 2.99mil+mdWirePad = 2.99mil+mdWireVia = 2.99mil+mdPadPad = 5.91mil+mdPadVia = 2.99mil+mdViaVia = 2.99mil+mdSmdPad = 2.99mil+mdSmdVia = 2.99mil+mdSmdSmd = 2.99mil+mdCopperDimension = 11.81mil+mdDrill = 7.87mil+msWidth = 2.99mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.09mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.09mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.09mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.09mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/allpcb-advanced-4L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="allpcb-advanced-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.076mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.076mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.076mm"/>+<param name="mdWirePad" value="0.076mm"/>+<param name="mdWireVia" value="0.076mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.076mm"/>+<param name="mdViaVia" value="0.076mm"/>+<param name="mdSmdPad" value="0.076mm"/>+<param name="mdSmdVia" value="0.076mm"/>+<param name="mdSmdSmd" value="0.076mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.076mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">ALLPCB 4-layer design rules (advanced process)++Min trace width: 0.076 mm (3.0 mil) - 1oz copper+Min spacing: 0.076 mm (3.0 mil) - 1oz copper+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.18 mm+Copper to board edge: 0.3 mm+Board thickness options: 0.4 mm, 4.0 mm+Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating+Max board size: 630 x 520 mm++Multi-layer board via/pad: 0.15mm inner diameter, 0.25mm outer diameter. Other limits as 2 layer entry.++Sources:+- https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.18mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.18mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.18mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.18mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/allpcb-advanced-6L.druadded+71@@ -0,0 +1,71 @@+description[ALLPCB 6-layer design rules (advanced process) | | Min trace width: 0.076 mm (3.0 mil) - 1oz copper | Min spacing: 0.076 mm (3.0 mil) - 1oz copper | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.18 mm | Copper to board edge: 0.3 mm | Board thickness options: 0.6 mm, 4.0 mm | Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz | Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating | Max board size: 630 x 520 mm | | 6 layer board thickness range 0.6 to 4.0mm, differs from 2 and 4 layer range 0.4 to 4.0mm. Other limits as 4 layer entry. | | Sources: | - https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 2.99mil+mdWirePad = 2.99mil+mdWireVia = 2.99mil+mdPadPad = 5.91mil+mdPadVia = 2.99mil+mdViaVia = 2.99mil+mdSmdPad = 2.99mil+mdSmdVia = 2.99mil+mdSmdSmd = 2.99mil+mdCopperDimension = 11.81mil+mdDrill = 7.87mil+msWidth = 2.99mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.09mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.09mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.09mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.09mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/allpcb-advanced-6L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="allpcb-advanced-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.076mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.076mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.076mm" preferredvalue="0.152mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.076mm"/>+<param name="mdWirePad" value="0.076mm"/>+<param name="mdWireVia" value="0.076mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.076mm"/>+<param name="mdViaVia" value="0.076mm"/>+<param name="mdSmdPad" value="0.076mm"/>+<param name="mdSmdVia" value="0.076mm"/>+<param name="mdSmdSmd" value="0.076mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.076mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">ALLPCB 6-layer design rules (advanced process)++Min trace width: 0.076 mm (3.0 mil) - 1oz copper+Min spacing: 0.076 mm (3.0 mil) - 1oz copper+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.18 mm+Copper to board edge: 0.3 mm+Board thickness options: 0.6 mm, 4.0 mm+Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating+Max board size: 630 x 520 mm++6 layer board thickness range 0.6 to 4.0mm, differs from 2 and 4 layer range 0.4 to 4.0mm. Other limits as 4 layer entry.++Sources:+- https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.18mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.18mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.18mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.18mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/elecrow-2L.druadded+71@@ -0,0 +1,71 @@+description[Elecrow 2-layer design rules (standard process) | | Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil | Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm) | Min drill: 0.3 mm (11.81 mil) | Min via: 0.3 mm hole | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm | Copper weight options: 1 oz, 2 oz | Surface finishes: HASL, HASL Lead Free, ENIG | Max board size: 550 x 550 mm | | Specs apply to regular custom PCB online ordering service, 1 to 8 layers share these limits. Maximum size 55cm x 55cm, minimum board dimension 10mm. Inner layer copper 17um (0.5 oz) or 35um (1 oz). Order form also offers OSP finish, 2.5mm thickness, and min castellated hole 0.60mm. Drill tolerance plated 0.1mm, non-plated 0.05mm. Outline tolerance plus or minus 0.20mm. Min silkscreen text height 0.8mm. | | Sources: | - https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 6.0mil+mdWirePad = 6.0mil+mdWireVia = 6.0mil+mdPadPad = 6.0mil+mdPadVia = 6.0mil+mdViaVia = 6.0mil+mdSmdPad = 6.0mil+mdSmdVia = 6.0mil+mdSmdSmd = 6.0mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 6.0mil+msDrill = 11.81mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/elecrow-2L.edruadded+141@@ -0,0 +1,141 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="elecrow-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1524mm" preferredvalue="0.4572mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1524mm" preferredvalue="0.3048mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.3mm" preferredvalue="0.6mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.3mm" preferredvalue="0.6mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1524mm"/>+<param name="mdWirePad" value="0.1524mm"/>+<param name="mdWireVia" value="0.1524mm"/>+<param name="mdPadPad" value="0.1524mm"/>+<param name="mdPadVia" value="0.1524mm"/>+<param name="mdViaVia" value="0.1524mm"/>+<param name="mdSmdPad" value="0.1524mm"/>+<param name="mdSmdVia" value="0.1524mm"/>+<param name="mdSmdSmd" value="0.1524mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.1524mm"/>+<param name="msDrill" value="0.3mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Elecrow 2-layer design rules (standard process)++Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil+Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)+Min drill: 0.3 mm (11.81 mil)+Min via: 0.3 mm hole+Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+Copper weight options: 1 oz, 2 oz+Surface finishes: HASL, HASL Lead Free, ENIG+Max board size: 550 x 550 mm++Specs apply to regular custom PCB online ordering service, 1 to 8 layers share these limits. Maximum size 55cm x 55cm, minimum board dimension 10mm. Inner layer copper 17um (0.5 oz) or 35um (1 oz). Order form also offers OSP finish, 2.5mm thickness, and min castellated hole 0.60mm. Drill tolerance plated 0.1mm, non-plated 0.05mm. Outline tolerance plus or minus 0.20mm. Min silkscreen text height 0.8mm.++Sources:+- https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/elecrow-4L.druadded+71@@ -0,0 +1,71 @@+description[Elecrow 4-layer design rules (standard process) | | Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil | Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm) | Min drill: 0.3 mm (11.81 mil) | Min via: 0.3 mm hole | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm | Copper weight options: 1 oz, 2 oz | Surface finishes: HASL, HASL Lead Free, ENIG | Max board size: 550 x 550 mm | | Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. 4 layer adds two inner layers (G1, G2 gerbers). Inner layer copper 17um (0.5 oz) or 35um (1 oz). | | Sources: | - https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 6.0mil+mdWirePad = 6.0mil+mdWireVia = 6.0mil+mdPadPad = 6.0mil+mdPadVia = 6.0mil+mdViaVia = 6.0mil+mdSmdPad = 6.0mil+mdSmdVia = 6.0mil+mdSmdSmd = 6.0mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 6.0mil+msDrill = 11.81mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/elecrow-4L.edruadded+141@@ -0,0 +1,141 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="elecrow-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1524mm" preferredvalue="0.4572mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1524mm" preferredvalue="0.3048mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.3mm" preferredvalue="0.6mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.3mm" preferredvalue="0.6mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1524mm"/>+<param name="mdWirePad" value="0.1524mm"/>+<param name="mdWireVia" value="0.1524mm"/>+<param name="mdPadPad" value="0.1524mm"/>+<param name="mdPadVia" value="0.1524mm"/>+<param name="mdViaVia" value="0.1524mm"/>+<param name="mdSmdPad" value="0.1524mm"/>+<param name="mdSmdVia" value="0.1524mm"/>+<param name="mdSmdSmd" value="0.1524mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.1524mm"/>+<param name="msDrill" value="0.3mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Elecrow 4-layer design rules (standard process)++Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil+Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)+Min drill: 0.3 mm (11.81 mil)+Min via: 0.3 mm hole+Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+Copper weight options: 1 oz, 2 oz+Surface finishes: HASL, HASL Lead Free, ENIG+Max board size: 550 x 550 mm++Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. 4 layer adds two inner layers (G1, G2 gerbers). Inner layer copper 17um (0.5 oz) or 35um (1 oz).++Sources:+- https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/elecrow-6L.druadded+71@@ -0,0 +1,71 @@+description[Elecrow 6-layer design rules (standard process) | | Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil | Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm) | Min drill: 0.3 mm (11.81 mil) | Min via: 0.3 mm hole | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm | Copper weight options: 1 oz, 2 oz | Surface finishes: HASL, HASL Lead Free, ENIG | Max board size: 550 x 550 mm | | Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. Inner layer copper 17um (0.5 oz) or 35um (1 oz). | | Sources: | - https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 6.0mil+mdWirePad = 6.0mil+mdWireVia = 6.0mil+mdPadPad = 6.0mil+mdPadVia = 6.0mil+mdViaVia = 6.0mil+mdSmdPad = 6.0mil+mdSmdVia = 6.0mil+mdSmdSmd = 6.0mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 6.0mil+msDrill = 11.81mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/elecrow-6L.edruadded+141@@ -0,0 +1,141 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="elecrow-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1524mm" preferredvalue="0.4572mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1524mm" preferredvalue="0.3048mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.3mm" preferredvalue="0.6mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.3mm" preferredvalue="0.6mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1524mm"/>+<param name="mdWirePad" value="0.1524mm"/>+<param name="mdWireVia" value="0.1524mm"/>+<param name="mdPadPad" value="0.1524mm"/>+<param name="mdPadVia" value="0.1524mm"/>+<param name="mdViaVia" value="0.1524mm"/>+<param name="mdSmdPad" value="0.1524mm"/>+<param name="mdSmdVia" value="0.1524mm"/>+<param name="mdSmdSmd" value="0.1524mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.1524mm"/>+<param name="msDrill" value="0.3mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Elecrow 6-layer design rules (standard process)++Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil+Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)+Min drill: 0.3 mm (11.81 mil)+Min via: 0.3 mm hole+Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+Copper weight options: 1 oz, 2 oz+Surface finishes: HASL, HASL Lead Free, ENIG+Max board size: 550 x 550 mm++Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. Inner layer copper 17um (0.5 oz) or 35um (1 oz).++Sources:+- https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/eurocircuits-2L.druadded+71@@ -0,0 +1,71 @@+description[Eurocircuits 2-layer design rules (standard process) | | Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil) | Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); pattern class table: class 6 track/gap 0.150 mm (5.9055 mil), class 7 0.125 mm (4.9213 mil), class 8 0.100 mm (3.937 mil), class 9 0.090 mm (3.5433 mil), class 5 0.175 mm (6.8898 mil) | Min drill: 0.1 mm (3.94 mil) | Min via: 0.1 mm hole / 0.4 mm pad | Annular ring: via 0.125 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.25 mm | Board thickness options: 1.0 mm, 1.55 mm, 2.4 mm | Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz | Surface finishes: ENIG, LF HAL, Immersion Silver | Max board size: 580 x 425 mm | | Min board 5 x 5 mm. Base copper foil pooling 2 layer: 12 µm (0.33 oz), 18 µm (0.5 oz), 35 µm (1 oz), 70 µm (2 oz); inner layers 18 µm and 35 µm. Minimum pad diameter: outer PTH finished hole plus 0.300 mm, outer NPTH plus 0.200 mm, inner PTH plus 0.350 mm, inner NPTH plus 0.250 mm. Classification min pattern values also limited by base copper foil: 12 µm 0.090 mm (3.5 mil), 18 µm 0.100 mm (4 mil), 35 µm 0.125 mm (5 mil), 70 µm 0.200 mm (8 mil), 105 µm 0.250 mm (10 mil), for both outer and inner layers. Drill class minimum TOOLSIZE: class A 0.60 mm (23.622 mil), B 0.45 mm (17.7165 mil), C 0.35 mm (13.7795 mil), D 0.25 mm (9.8425 mil), E 0.20 mm (7.874 mil); max board thickness per drill class: A and B 3.20 mm, C 2.40 mm, D 2.00 mm, E 1.60 mm; aspect ratio 1:8. TOOLSIZE equals finished PTH size plus 0.10 mm (4 mil). Soldermask colors pooling: green, blue, black, white, red; non-pooling transparent. Legend white one or both sides, non-pooling black and white. | | Sources: | - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03) | - https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.94mil+mdWirePad = 3.94mil+mdWireVia = 3.94mil+mdPadPad = 5.91mil+mdPadVia = 3.94mil+mdViaVia = 3.94mil+mdSmdPad = 3.94mil+mdSmdVia = 3.94mil+mdSmdSmd = 3.94mil+mdCopperDimension = 9.84mil+mdDrill = 9.84mil+msWidth = 3.94mil+msDrill = 3.94mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.92mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.92mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.92mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.92mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/eurocircuits-2L.edruadded+146@@ -0,0 +1,146 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="eurocircuits-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1mm" preferredvalue="0.2mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1mm" preferredvalue="0.25mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.25mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1mm"/>+<param name="mdWirePad" value="0.1mm"/>+<param name="mdWireVia" value="0.1mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1mm"/>+<param name="mdViaVia" value="0.1mm"/>+<param name="mdSmdPad" value="0.1mm"/>+<param name="mdSmdVia" value="0.1mm"/>+<param name="mdSmdSmd" value="0.1mm"/>+<param name="mdCopperDimension" value="0.25mm"/>+<param name="mdDrill" value="0.25mm"/>+<param name="msWidth" value="0.1mm"/>+<param name="msDrill" value="0.1mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Eurocircuits 2-layer design rules (standard process)++Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)+Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); pattern class table: class 6 track/gap 0.150 mm (5.9055 mil), class 7 0.125 mm (4.9213 mil), class 8 0.100 mm (3.937 mil), class 9 0.090 mm (3.5433 mil), class 5 0.175 mm (6.8898 mil)+Min drill: 0.1 mm (3.94 mil)+Min via: 0.1 mm hole / 0.4 mm pad+Annular ring: via 0.125 mm+Copper to board edge: 0.25 mm+Hole to hole: 0.25 mm+Board thickness options: 1.0 mm, 1.55 mm, 2.4 mm+Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz+Surface finishes: ENIG, LF HAL, Immersion Silver+Max board size: 580 x 425 mm++Min board 5 x 5 mm. Base copper foil pooling 2 layer: 12 µm (0.33 oz), 18 µm (0.5 oz), 35 µm (1 oz), 70 µm (2 oz); inner layers 18 µm and 35 µm. Minimum pad diameter: outer PTH finished hole plus 0.300 mm, outer NPTH plus 0.200 mm, inner PTH plus 0.350 mm, inner NPTH plus 0.250 mm. Classification min pattern values also limited by base copper foil: 12 µm 0.090 mm (3.5 mil), 18 µm 0.100 mm (4 mil), 35 µm 0.125 mm (5 mil), 70 µm 0.200 mm (8 mil), 105 µm 0.250 mm (10 mil), for both outer and inner layers. Drill class minimum TOOLSIZE: class A 0.60 mm (23.622 mil), B 0.45 mm (17.7165 mil), C 0.35 mm (13.7795 mil), D 0.25 mm (9.8425 mil), E 0.20 mm (7.874 mil); max board thickness per drill class: A and B 3.20 mm, C 2.40 mm, D 2.00 mm, E 1.60 mm; aspect ratio 1:8. TOOLSIZE equals finished PTH size plus 0.10 mm (4 mil). Soldermask colors pooling: green, blue, black, white, red; non-pooling transparent. Legend white one or both sides, non-pooling black and white.++Sources:+- https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)+- https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)+- https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.125mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.125mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.125mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.125mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/eurocircuits-4L.druadded+71@@ -0,0 +1,71 @@+description[Eurocircuits 4-layer design rules (standard process) | | Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); inner layer same classification values | Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); pattern class 6 is 0.150 mm (5.9055 mil) | Min drill: 0.1 mm (3.94 mil) | Min via: 0.1 mm hole / 0.4 mm pad | Annular ring: via 0.125 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.25 mm | Board thickness options: 1.0 mm, 1.55 mm | Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz | Surface finishes: ENIG, LF HAL, Immersion Silver | Max board size: 500 x 425 mm | | 4 layer pooling board thickness 1.00 mm; 1.55 mm pooling for 6 to 16 layers. Multilayer max dimension 500 x 425 mm. Standard buildups pooled, 8 predefined non-pooling builds; blind and buried vias non-pooling specials. Base copper inner layers pooling 18 µm and 35 µm. | | Sources: | - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.94mil+mdWirePad = 3.94mil+mdWireVia = 3.94mil+mdPadPad = 5.91mil+mdPadVia = 3.94mil+mdViaVia = 3.94mil+mdSmdPad = 3.94mil+mdSmdVia = 3.94mil+mdSmdSmd = 3.94mil+mdCopperDimension = 9.84mil+mdDrill = 9.84mil+msWidth = 3.94mil+msDrill = 3.94mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.92mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.92mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.92mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.92mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/eurocircuits-4L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="eurocircuits-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1mm" preferredvalue="0.2mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1mm" preferredvalue="0.25mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.25mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1mm"/>+<param name="mdWirePad" value="0.1mm"/>+<param name="mdWireVia" value="0.1mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1mm"/>+<param name="mdViaVia" value="0.1mm"/>+<param name="mdSmdPad" value="0.1mm"/>+<param name="mdSmdVia" value="0.1mm"/>+<param name="mdSmdSmd" value="0.1mm"/>+<param name="mdCopperDimension" value="0.25mm"/>+<param name="mdDrill" value="0.25mm"/>+<param name="msWidth" value="0.1mm"/>+<param name="msDrill" value="0.1mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Eurocircuits 4-layer design rules (standard process)++Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); inner layer same classification values+Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); pattern class 6 is 0.150 mm (5.9055 mil)+Min drill: 0.1 mm (3.94 mil)+Min via: 0.1 mm hole / 0.4 mm pad+Annular ring: via 0.125 mm+Copper to board edge: 0.25 mm+Hole to hole: 0.25 mm+Board thickness options: 1.0 mm, 1.55 mm+Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz+Surface finishes: ENIG, LF HAL, Immersion Silver+Max board size: 500 x 425 mm++4 layer pooling board thickness 1.00 mm; 1.55 mm pooling for 6 to 16 layers. Multilayer max dimension 500 x 425 mm. Standard buildups pooled, 8 predefined non-pooling builds; blind and buried vias non-pooling specials. Base copper inner layers pooling 18 µm and 35 µm.++Sources:+- https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)+- https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.125mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.125mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.125mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.125mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/eurocircuits-6L.druadded+71@@ -0,0 +1,71 @@+description[Eurocircuits 6-layer design rules (standard process) | | Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil) | Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil) | Min drill: 0.1 mm (3.94 mil) | Min via: 0.1 mm hole / 0.4 mm pad | Annular ring: via 0.125 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.25 mm | Board thickness options: 1.55 mm | Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz | Surface finishes: ENIG, LF HAL, Immersion Silver | Max board size: 500 x 425 mm | | 6 and 8 layers pooling in STANDARD pool; 10 to 16 layers non-pooling. Pooling board thickness for multilayers 6 layers and above is 1.55 mm. Same pattern and drill classification system applies. | | Sources: | - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.94mil+mdWirePad = 3.94mil+mdWireVia = 3.94mil+mdPadPad = 5.91mil+mdPadVia = 3.94mil+mdViaVia = 3.94mil+mdSmdPad = 3.94mil+mdSmdVia = 3.94mil+mdSmdSmd = 3.94mil+mdCopperDimension = 9.84mil+mdDrill = 9.84mil+msWidth = 3.94mil+msDrill = 3.94mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.92mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.92mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.92mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.92mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/eurocircuits-6L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="eurocircuits-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1mm" preferredvalue="0.2mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1mm" preferredvalue="0.25mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.25mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1mm"/>+<param name="mdWirePad" value="0.1mm"/>+<param name="mdWireVia" value="0.1mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1mm"/>+<param name="mdViaVia" value="0.1mm"/>+<param name="mdSmdPad" value="0.1mm"/>+<param name="mdSmdVia" value="0.1mm"/>+<param name="mdSmdSmd" value="0.1mm"/>+<param name="mdCopperDimension" value="0.25mm"/>+<param name="mdDrill" value="0.25mm"/>+<param name="msWidth" value="0.1mm"/>+<param name="msDrill" value="0.1mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Eurocircuits 6-layer design rules (standard process)++Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)+Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)+Min drill: 0.1 mm (3.94 mil)+Min via: 0.1 mm hole / 0.4 mm pad+Annular ring: via 0.125 mm+Copper to board edge: 0.25 mm+Hole to hole: 0.25 mm+Board thickness options: 1.55 mm+Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz+Surface finishes: ENIG, LF HAL, Immersion Silver+Max board size: 500 x 425 mm++6 and 8 layers pooling in STANDARD pool; 10 to 16 layers non-pooling. Pooling board thickness for multilayers 6 layers and above is 1.55 mm. Same pattern and drill classification system applies.++Sources:+- https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.125mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.125mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.125mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.125mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/eurocircuits-proto-2L.druadded+71@@ -0,0 +1,71 @@+description[Eurocircuits 2-layer design rules (proto process) | | Min trace width: 0.15 mm (5.91 mil) - all services, pattern class 6 | Min spacing: 0.15 mm (5.91 mil) - track to track, pattern class 6; class 5 is 0.175 mm (6.8898 mil), class 7 is 0.125 mm (4.9213 mil) | Min drill: 0.25 mm (9.84 mil) | Min via: 0.25 mm hole / 0.6 mm pad | Annular ring: via 0.125 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.25 mm | Board thickness options: 1.55 mm | Copper weight options: 0.5 oz, 1 oz | Surface finishes: ENIG, LF HAL | Max board size: 580 x 425 mm | | Min board 20 x 20 mm. Base copper foil: outer layers 18 µm (0.5 oz), inner layers 35 µm (1 oz). Minimum pad diameter: PTH is finished hole plus 0.350 mm on outer and inner layers, NPTH is finished hole plus 0.250 mm. Tool size equals finished PTH hole size plus 0.10 mm (4 mil), NPTH tool size equals finished size. Drill bits in 0.05 mm increments. Standard PTH hole tolerance plus/minus 0.10 mm (0.20 mm range) for holes 4 mm or less, NPTH plus/minus 0.05 mm. Holes with finished size 0.45 mm or smaller are defined as via holes. Pattern class 5 (all services): track/gap 0.175 mm (6.8898 mil), OAR/IAR 0.150 mm (5.9055 mil), IPI 0.225 mm (8.8583 mil). Legend to board edge: 0.250 mm routing, 0.450 mm scoring. Soldermask design rules LDI: pad to pad 0.135 mm (5.315 mil), track to pad 0.090 mm (3.5433 mil); PI colors: pad to pad 0.330 mm (12.9921 mil), track to pad 0.190 mm (7.4803 mil). Mask overlap clearance MOC: LDI 0.060 mm (2.3622 mil), PI 0.090 mm (3.5433 mil). | | Sources: | - https://www.eurocircuits.com/services/pcb-proto/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03) | - https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/drilled-holes/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/soldermask/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/legend-print/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/copper-layers/ (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.91mil+mdWirePad = 5.91mil+mdWireVia = 5.91mil+mdPadPad = 5.91mil+mdPadVia = 5.91mil+mdViaVia = 5.91mil+mdSmdPad = 5.91mil+mdSmdVia = 5.91mil+mdSmdSmd = 5.91mil+mdCopperDimension = 9.84mil+mdDrill = 9.84mil+msWidth = 5.91mil+msDrill = 9.84mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.92mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.92mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.92mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.92mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/eurocircuits-proto-2L.edruadded+150@@ -0,0 +1,150 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="eurocircuits-proto-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.15mm" preferredvalue="0.45mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.15mm" preferredvalue="0.3mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.25mm" preferredvalue="0.5mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.25mm" preferredvalue="0.5mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.25mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.15mm"/>+<param name="mdWirePad" value="0.15mm"/>+<param name="mdWireVia" value="0.15mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.15mm"/>+<param name="mdViaVia" value="0.15mm"/>+<param name="mdSmdPad" value="0.15mm"/>+<param name="mdSmdVia" value="0.15mm"/>+<param name="mdSmdSmd" value="0.15mm"/>+<param name="mdCopperDimension" value="0.25mm"/>+<param name="mdDrill" value="0.25mm"/>+<param name="msWidth" value="0.15mm"/>+<param name="msDrill" value="0.25mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Eurocircuits 2-layer design rules (proto process)++Min trace width: 0.15 mm (5.91 mil) - all services, pattern class 6+Min spacing: 0.15 mm (5.91 mil) - track to track, pattern class 6; class 5 is 0.175 mm (6.8898 mil), class 7 is 0.125 mm (4.9213 mil)+Min drill: 0.25 mm (9.84 mil)+Min via: 0.25 mm hole / 0.6 mm pad+Annular ring: via 0.125 mm+Copper to board edge: 0.25 mm+Hole to hole: 0.25 mm+Board thickness options: 1.55 mm+Copper weight options: 0.5 oz, 1 oz+Surface finishes: ENIG, LF HAL+Max board size: 580 x 425 mm++Min board 20 x 20 mm. Base copper foil: outer layers 18 µm (0.5 oz), inner layers 35 µm (1 oz). Minimum pad diameter: PTH is finished hole plus 0.350 mm on outer and inner layers, NPTH is finished hole plus 0.250 mm. Tool size equals finished PTH hole size plus 0.10 mm (4 mil), NPTH tool size equals finished size. Drill bits in 0.05 mm increments. Standard PTH hole tolerance plus/minus 0.10 mm (0.20 mm range) for holes 4 mm or less, NPTH plus/minus 0.05 mm. Holes with finished size 0.45 mm or smaller are defined as via holes. Pattern class 5 (all services): track/gap 0.175 mm (6.8898 mil), OAR/IAR 0.150 mm (5.9055 mil), IPI 0.225 mm (8.8583 mil). Legend to board edge: 0.250 mm routing, 0.450 mm scoring. Soldermask design rules LDI: pad to pad 0.135 mm (5.315 mil), track to pad 0.090 mm (3.5433 mil); PI colors: pad to pad 0.330 mm (12.9921 mil), track to pad 0.190 mm (7.4803 mil). Mask overlap clearance MOC: LDI 0.060 mm (2.3622 mil), PI 0.090 mm (3.5433 mil).++Sources:+- https://www.eurocircuits.com/services/pcb-proto/ (read 2026-09-03)+- https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)+- https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png (read 2026-09-03)+- https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/drilled-holes/ (read 2026-09-03)+- https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/soldermask/ (read 2026-09-03)+- https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/legend-print/ (read 2026-09-03)+- https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/copper-layers/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.125mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.125mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.125mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.125mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/eurocircuits-proto-4L.druadded+71@@ -0,0 +1,71 @@+description[Eurocircuits 4-layer design rules (proto process) | | Min trace width: 0.15 mm (5.91 mil) - outer and inner layers, pattern class 6 | Min spacing: 0.15 mm (5.91 mil) - pattern class 6; class 5 is 0.175 mm (6.8898 mil) | Min drill: 0.25 mm (9.84 mil) | Min via: 0.25 mm hole / 0.6 mm pad | Annular ring: via 0.125 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.25 mm | Board thickness options: 1.55 mm | Copper weight options: 0.5 oz, 1 oz | Surface finishes: ENIG, LF HAL | Max board size: 500 x 425 mm | | 4 layer max board size 500 x 425 mm. Same build parameters as 2 layer. Blind and buried vias not available in PCB proto. | | Sources: | - https://www.eurocircuits.com/services/pcb-proto/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.91mil+mdWirePad = 5.91mil+mdWireVia = 5.91mil+mdPadPad = 5.91mil+mdPadVia = 5.91mil+mdViaVia = 5.91mil+mdSmdPad = 5.91mil+mdSmdVia = 5.91mil+mdSmdSmd = 5.91mil+mdCopperDimension = 9.84mil+mdDrill = 9.84mil+msWidth = 5.91mil+msDrill = 9.84mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.92mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.92mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.92mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.92mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/eurocircuits-proto-4L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="eurocircuits-proto-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.15mm" preferredvalue="0.45mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.15mm" preferredvalue="0.3mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.25mm" preferredvalue="0.5mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.25mm" preferredvalue="0.5mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.15mm" preferredvalue="0.3mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.25mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.15mm"/>+<param name="mdWirePad" value="0.15mm"/>+<param name="mdWireVia" value="0.15mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.15mm"/>+<param name="mdViaVia" value="0.15mm"/>+<param name="mdSmdPad" value="0.15mm"/>+<param name="mdSmdVia" value="0.15mm"/>+<param name="mdSmdSmd" value="0.15mm"/>+<param name="mdCopperDimension" value="0.25mm"/>+<param name="mdDrill" value="0.25mm"/>+<param name="msWidth" value="0.15mm"/>+<param name="msDrill" value="0.25mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Eurocircuits 4-layer design rules (proto process)++Min trace width: 0.15 mm (5.91 mil) - outer and inner layers, pattern class 6+Min spacing: 0.15 mm (5.91 mil) - pattern class 6; class 5 is 0.175 mm (6.8898 mil)+Min drill: 0.25 mm (9.84 mil)+Min via: 0.25 mm hole / 0.6 mm pad+Annular ring: via 0.125 mm+Copper to board edge: 0.25 mm+Hole to hole: 0.25 mm+Board thickness options: 1.55 mm+Copper weight options: 0.5 oz, 1 oz+Surface finishes: ENIG, LF HAL+Max board size: 500 x 425 mm++4 layer max board size 500 x 425 mm. Same build parameters as 2 layer. Blind and buried vias not available in PCB proto.++Sources:+- https://www.eurocircuits.com/services/pcb-proto/ (read 2026-09-03)+- https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.125mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.125mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.125mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.125mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/jlcpcb-2L.druadded+71@@ -0,0 +1,71 @@+description[JLCPCB 2-layer design rules (standard process) | | Min trace width: 0.1 mm (4.0 mil) - 1 oz copper outer layer | Min spacing: 0.1 mm (4.0 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm | Copper weight options: 1 oz, 2 oz, 2.5 oz, 3.5 oz, 4.5 oz | Surface finishes: HASL leaded, HASL lead-free, ENIG | Max board size: 670 x 600 mm | | 2 oz: min trace/spacing 0.16/0.16 mm (6.5/6.5 mil). 2.5 oz: 0.2/0.2 mm (8/8 mil). 3.5 oz: 0.25/0.25 mm (10/10 mil). 4.5 oz: 0.3/0.3 mm (12/12 mil). Min drill 0.15 mm costs more. Via diameter should be 0.1 mm (0.15 mm preferred) larger than via hole, preferred min via hole 0.2 mm. PTH annular ring 2 oz: 0.254 mm or above. NPTH pad annular ring 0.45 mm recommended. Min NPTH 0.5 mm. Min plated slot width 0.5 mm. Pad to track clearance 0.1 mm. SMD pad to pad clearance different nets 0.15 mm. Via hole to track 0.2 mm, PTH to track 0.28 mm (0.35 recommended), NPTH to track 0.2 mm. Same-net track spacing 0.25 mm. Min silk text height 1.0 mm (40 mil). Soldermask opening to neighboring trace clearance 0.09 mm. Trace width tolerance plus/minus 20 percent. | | Sources: | - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.94mil+mdWirePad = 3.94mil+mdWireVia = 3.94mil+mdPadPad = 5.91mil+mdPadVia = 3.94mil+mdViaVia = 3.94mil+mdSmdPad = 3.94mil+mdSmdVia = 3.94mil+mdSmdSmd = 3.94mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 3.94mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 7.09mil+rlMaxViaOuter = 20mil+rlMinViaInner = 7.09mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 7.09mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 7.09mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/jlcpcb-2L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="jlcpcb-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1mm" preferredvalue="0.2mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1mm"/>+<param name="mdWirePad" value="0.1mm"/>+<param name="mdWireVia" value="0.1mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1mm"/>+<param name="mdViaVia" value="0.1mm"/>+<param name="mdSmdPad" value="0.1mm"/>+<param name="mdSmdVia" value="0.1mm"/>+<param name="mdSmdSmd" value="0.1mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.1mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">JLCPCB 2-layer design rules (standard process)++Min trace width: 0.1 mm (4.0 mil) - 1 oz copper outer layer+Min spacing: 0.1 mm (4.0 mil) - 1 oz copper, different nets+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.18 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.2 mm+Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+Copper weight options: 1 oz, 2 oz, 2.5 oz, 3.5 oz, 4.5 oz+Surface finishes: HASL leaded, HASL lead-free, ENIG+Max board size: 670 x 600 mm++2 oz: min trace/spacing 0.16/0.16 mm (6.5/6.5 mil). 2.5 oz: 0.2/0.2 mm (8/8 mil). 3.5 oz: 0.25/0.25 mm (10/10 mil). 4.5 oz: 0.3/0.3 mm (12/12 mil). Min drill 0.15 mm costs more. Via diameter should be 0.1 mm (0.15 mm preferred) larger than via hole, preferred min via hole 0.2 mm. PTH annular ring 2 oz: 0.254 mm or above. NPTH pad annular ring 0.45 mm recommended. Min NPTH 0.5 mm. Min plated slot width 0.5 mm. Pad to track clearance 0.1 mm. SMD pad to pad clearance different nets 0.15 mm. Via hole to track 0.2 mm, PTH to track 0.28 mm (0.35 recommended), NPTH to track 0.2 mm. Same-net track spacing 0.25 mm. Min silk text height 1.0 mm (40 mil). Soldermask opening to neighboring trace clearance 0.09 mm. Trace width tolerance plus/minus 20 percent.++Sources:+- https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.18mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.18mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.18mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.18mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/jlcpcb-4L.druadded+71@@ -0,0 +1,71 @@+description[JLCPCB 4-layer design rules (standard process) | | Min trace width: 0.09 mm (3.5 mil) - 1 oz copper outer layer, 3 mil acceptable in BGA fan-outs | Min spacing: 0.09 mm (3.5 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.15 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm | Copper weight options: 1 oz, 2 oz | Surface finishes: HASL leaded, HASL lead-free, ENIG | Max board size: 663 x 593 mm | | Same source page as 2 layer, multilayer column. Inner layer copper 0.5/1/2 oz, 0.5 oz default. Inner layer via hole to copper clearance 0.2 mm, inner PTH pad hole to copper clearance 0.3 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Min plated slot width 0.35 mm multilayer. Controlled impedance available. Blind/buried vias not supported, through holes only. | | Sources: | - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.54mil+mdWirePad = 3.54mil+mdWireVia = 3.54mil+mdPadPad = 5.91mil+mdPadVia = 3.54mil+mdViaVia = 3.54mil+mdSmdPad = 3.54mil+mdSmdVia = 3.54mil+mdSmdSmd = 3.54mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 3.54mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.91mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.91mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.91mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.91mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/jlcpcb-4L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="jlcpcb-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.09mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.09mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.09mm"/>+<param name="mdWirePad" value="0.09mm"/>+<param name="mdWireVia" value="0.09mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.09mm"/>+<param name="mdViaVia" value="0.09mm"/>+<param name="mdSmdPad" value="0.09mm"/>+<param name="mdSmdVia" value="0.09mm"/>+<param name="mdSmdSmd" value="0.09mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.09mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">JLCPCB 4-layer design rules (standard process)++Min trace width: 0.09 mm (3.5 mil) - 1 oz copper outer layer, 3 mil acceptable in BGA fan-outs+Min spacing: 0.09 mm (3.5 mil) - 1 oz copper, different nets+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.15 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.2 mm+Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+Copper weight options: 1 oz, 2 oz+Surface finishes: HASL leaded, HASL lead-free, ENIG+Max board size: 663 x 593 mm++Same source page as 2 layer, multilayer column. Inner layer copper 0.5/1/2 oz, 0.5 oz default. Inner layer via hole to copper clearance 0.2 mm, inner PTH pad hole to copper clearance 0.3 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Min plated slot width 0.35 mm multilayer. Controlled impedance available. Blind/buried vias not supported, through holes only.++Sources:+- https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.15mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.15mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.15mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.15mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/jlcpcb-6L.druadded+71@@ -0,0 +1,71 @@+description[JLCPCB 6-layer design rules (standard process) | | Min trace width: 0.09 mm (3.5 mil) - 1 oz copper outer layer, 3 mil acceptable in BGA fan-outs | Min spacing: 0.09 mm (3.5 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.15 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm | Copper weight options: 1 oz, 2 oz | Surface finishes: ENIG | Max board size: 656 x 586 mm | | Same source page as 2 layer, multilayer column. 6 layer and above boards only have ENIG surface finish. Via-in-pad epoxy filled and capped is the default process for 6 layer and above boards, compatible with via diameters 0.15 to 0.55 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Backdrill supported on 4 to 32 layer FR4, thickness 0.8 mm or more. | | Sources: | - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.54mil+mdWirePad = 3.54mil+mdWireVia = 3.54mil+mdPadPad = 5.91mil+mdPadVia = 3.54mil+mdViaVia = 3.54mil+mdSmdPad = 3.54mil+mdSmdVia = 3.54mil+mdSmdSmd = 3.54mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 3.54mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.91mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.91mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.91mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.91mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/jlcpcb-6L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="jlcpcb-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.09mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.09mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.09mm" preferredvalue="0.18mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.09mm"/>+<param name="mdWirePad" value="0.09mm"/>+<param name="mdWireVia" value="0.09mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.09mm"/>+<param name="mdViaVia" value="0.09mm"/>+<param name="mdSmdPad" value="0.09mm"/>+<param name="mdSmdVia" value="0.09mm"/>+<param name="mdSmdSmd" value="0.09mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.09mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">JLCPCB 6-layer design rules (standard process)++Min trace width: 0.09 mm (3.5 mil) - 1 oz copper outer layer, 3 mil acceptable in BGA fan-outs+Min spacing: 0.09 mm (3.5 mil) - 1 oz copper, different nets+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.25 mm pad+Annular ring: via 0.15 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.2 mm+Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+Copper weight options: 1 oz, 2 oz+Surface finishes: ENIG+Max board size: 656 x 586 mm++Same source page as 2 layer, multilayer column. 6 layer and above boards only have ENIG surface finish. Via-in-pad epoxy filled and capped is the default process for 6 layer and above boards, compatible with via diameters 0.15 to 0.55 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Backdrill supported on 4 to 32 layer FR4, thickness 0.8 mm or more.++Sources:+- https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.15mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.15mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.15mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.15mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/macrofab-2L.druadded+71@@ -0,0 +1,71 @@+description[MacroFab 2-layer design rules (standard process) | | Min trace width: 0.127 mm (5.0 mil) - standard manufacturing specifications | Min spacing: 0.127 mm (5.0 mil) - standard manufacturing specifications | Min drill: 0.3048 mm (12.0 mil) | Min via: 0.3048 mm hole | Board thickness options: 1.6 mm | Copper weight options: 0.5 oz, 1 oz | Surface finishes: ENIG | Max board size: 378.46 x 378.46 mm | | Standard (default, non-extended) manufacturing specifications per MacroFab help article: minimum trace width 5 mil, minimum drill 12 mil; page notes the standard tier was later reduced (5 mil spacing, 10 mil drill announced December 2018) but the help article body was only visible via search index, not fully readable on load. | | Sources: | - https://support.macrofab.com/s/article/pcb-specifications-and-drc (read 2026-09-03) | - https://support.macrofab.com/s/article/can-i-customize-my-pcb (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 5.0mil+msDrill = 12.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/macrofab-2L.edruadded+142@@ -0,0 +1,142 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="macrofab-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.127mm" preferredvalue="0.381mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.127mm" preferredvalue="0.254mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.3048mm" preferredvalue="0.6096mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.3048mm" preferredvalue="0.6096mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.127mm"/>+<param name="msDrill" value="0.3048mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">MacroFab 2-layer design rules (standard process)++Min trace width: 0.127 mm (5.0 mil) - standard manufacturing specifications+Min spacing: 0.127 mm (5.0 mil) - standard manufacturing specifications+Min drill: 0.3048 mm (12.0 mil)+Min via: 0.3048 mm hole+Board thickness options: 1.6 mm+Copper weight options: 0.5 oz, 1 oz+Surface finishes: ENIG+Max board size: 378.46 x 378.46 mm++Standard (default, non-extended) manufacturing specifications per MacroFab help article: minimum trace width 5 mil, minimum drill 12 mil; page notes the standard tier was later reduced (5 mil spacing, 10 mil drill announced December 2018) but the help article body was only visible via search index, not fully readable on load.++Sources:+- https://support.macrofab.com/s/article/pcb-specifications-and-drc (read 2026-09-03)+- https://support.macrofab.com/s/article/can-i-customize-my-pcb (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/macrofab-4L.druadded+71@@ -0,0 +1,71 @@+description[MacroFab 4-layer design rules (standard process) | | Min trace width: 0.127 mm (5.0 mil) - standard manufacturing specifications | Min spacing: 0.127 mm (5.0 mil) - standard manufacturing specifications | Min drill: 0.3048 mm (12.0 mil) | Min via: 0.3048 mm hole | Board thickness options: 1.6 mm | Copper weight options: 0.5 oz, 1 oz | Surface finishes: ENIG | Max board size: 378.46 x 378.46 mm | | Same standard specifications as 2-layer; help article does not differentiate by layer count. | | Sources: | - https://support.macrofab.com/s/article/pcb-specifications-and-drc (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 5.0mil+msDrill = 12.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/macrofab-4L.edruadded+141@@ -0,0 +1,141 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="macrofab-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.127mm" preferredvalue="0.381mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.127mm" preferredvalue="0.254mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.3048mm" preferredvalue="0.6096mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.3048mm" preferredvalue="0.6096mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.127mm"/>+<param name="msDrill" value="0.3048mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">MacroFab 4-layer design rules (standard process)++Min trace width: 0.127 mm (5.0 mil) - standard manufacturing specifications+Min spacing: 0.127 mm (5.0 mil) - standard manufacturing specifications+Min drill: 0.3048 mm (12.0 mil)+Min via: 0.3048 mm hole+Board thickness options: 1.6 mm+Copper weight options: 0.5 oz, 1 oz+Surface finishes: ENIG+Max board size: 378.46 x 378.46 mm++Same standard specifications as 2-layer; help article does not differentiate by layer count.++Sources:+- https://support.macrofab.com/s/article/pcb-specifications-and-drc (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/macrofab-extended-2L.druadded+71@@ -0,0 +1,71 @@+description[MacroFab 2-layer design rules (extended process) | | Min trace width: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper | Min spacing: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper | Min drill: 0.1016 mm (4.0 mil) | Min via: 0.1016 mm hole / 0.254 mm pad | Annular ring: via 0.0762 mm | Copper to board edge: 0.0762 mm | Hole to hole: 0.1524 mm | Board thickness options: 1.6 mm | Copper weight options: 0.5 oz, 1 oz | Surface finishes: ENIG | Max board size: 378.46 x 378.46 mm | | Extended DRC minimums as published. Board thickness 1.6 mm standard, other custom thicknesses supported; thickness tolerance T below 1.0 mm plus minus 15 percent, 1.0 to 1.6 mm plus minus 10 percent, T at or above 1.6 mm plus minus 10 percent. Min via pad derived from published min drill plus 2x annular ring: 4 mil plus 6 mil. NPTH hole size tolerance plus minus 0.05 mm, PTH plus minus 0.08 mm. Board edge tolerance plus minus 0.15 mm. Extended option disabled for 2 oz copper. Paste aperture min 0.1524 mm, paste clearance 0.1524 mm. Silkscreen text height min 0.8 mm. | | Sources: | - https://www.macrofab.com/capabilities/ (read 2026-09-03) | - https://www.macrofab.com/pcba/specs/ (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.0mil+mdWirePad = 3.0mil+mdWireVia = 3.0mil+mdPadPad = 5.91mil+mdPadVia = 3.0mil+mdViaVia = 3.0mil+mdSmdPad = 3.0mil+mdSmdVia = 3.0mil+mdSmdSmd = 3.0mil+mdCopperDimension = 3.0mil+mdDrill = 6.0mil+msWidth = 3.0mil+msDrill = 4.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/macrofab-extended-2L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="macrofab-extended-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0762mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0762mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1016mm" preferredvalue="0.2032mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1016mm" preferredvalue="0.25mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.0762mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.1524mm" preferredvalue="0.1524mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0762mm"/>+<param name="mdWirePad" value="0.0762mm"/>+<param name="mdWireVia" value="0.0762mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0762mm"/>+<param name="mdViaVia" value="0.0762mm"/>+<param name="mdSmdPad" value="0.0762mm"/>+<param name="mdSmdVia" value="0.0762mm"/>+<param name="mdSmdSmd" value="0.0762mm"/>+<param name="mdCopperDimension" value="0.0762mm"/>+<param name="mdDrill" value="0.1524mm"/>+<param name="msWidth" value="0.0762mm"/>+<param name="msDrill" value="0.1016mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">MacroFab 2-layer design rules (extended process)++Min trace width: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper+Min spacing: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper+Min drill: 0.1016 mm (4.0 mil)+Min via: 0.1016 mm hole / 0.254 mm pad+Annular ring: via 0.0762 mm+Copper to board edge: 0.0762 mm+Hole to hole: 0.1524 mm+Board thickness options: 1.6 mm+Copper weight options: 0.5 oz, 1 oz+Surface finishes: ENIG+Max board size: 378.46 x 378.46 mm++Extended DRC minimums as published. Board thickness 1.6 mm standard, other custom thicknesses supported; thickness tolerance T below 1.0 mm plus minus 15 percent, 1.0 to 1.6 mm plus minus 10 percent, T at or above 1.6 mm plus minus 10 percent. Min via pad derived from published min drill plus 2x annular ring: 4 mil plus 6 mil. NPTH hole size tolerance plus minus 0.05 mm, PTH plus minus 0.08 mm. Board edge tolerance plus minus 0.15 mm. Extended option disabled for 2 oz copper. Paste aperture min 0.1524 mm, paste clearance 0.1524 mm. Silkscreen text height min 0.8 mm.++Sources:+- https://www.macrofab.com/capabilities/ (read 2026-09-03)+- https://www.macrofab.com/pcba/specs/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0762mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0762mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0762mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0762mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/macrofab-extended-4L.druadded+71@@ -0,0 +1,71 @@+description[MacroFab 4-layer design rules (extended process) | | Min trace width: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper | Min spacing: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper | Min drill: 0.1016 mm (4.0 mil) | Min via: 0.1016 mm hole / 0.254 mm pad | Annular ring: via 0.0762 mm | Copper to board edge: 0.0762 mm | Hole to hole: 0.1524 mm | Board thickness options: 1.6 mm | Copper weight options: 0.5 oz, 1 oz | Surface finishes: ENIG | Max board size: 378.46 x 378.46 mm | | Same extended DRC table published for all layer counts; MacroFab supports 2 to 36 layer boards per capabilities page. 2 oz copper requires larger trace, spacing, annular ring and disables the extended option; specific 2 oz numbers not published on the read pages. | | Sources: | - https://www.macrofab.com/capabilities/ (read 2026-09-03) | - https://www.macrofab.com/pcba/specs/ (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.0mil+mdWirePad = 3.0mil+mdWireVia = 3.0mil+mdPadPad = 5.91mil+mdPadVia = 3.0mil+mdViaVia = 3.0mil+mdSmdPad = 3.0mil+mdSmdVia = 3.0mil+mdSmdSmd = 3.0mil+mdCopperDimension = 3.0mil+mdDrill = 6.0mil+msWidth = 3.0mil+msDrill = 4.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/macrofab-extended-4L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="macrofab-extended-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0762mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0762mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1016mm" preferredvalue="0.2032mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1016mm" preferredvalue="0.25mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.0762mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.1524mm" preferredvalue="0.1524mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0762mm"/>+<param name="mdWirePad" value="0.0762mm"/>+<param name="mdWireVia" value="0.0762mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0762mm"/>+<param name="mdViaVia" value="0.0762mm"/>+<param name="mdSmdPad" value="0.0762mm"/>+<param name="mdSmdVia" value="0.0762mm"/>+<param name="mdSmdSmd" value="0.0762mm"/>+<param name="mdCopperDimension" value="0.0762mm"/>+<param name="mdDrill" value="0.1524mm"/>+<param name="msWidth" value="0.0762mm"/>+<param name="msDrill" value="0.1016mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">MacroFab 4-layer design rules (extended process)++Min trace width: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper+Min spacing: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper+Min drill: 0.1016 mm (4.0 mil)+Min via: 0.1016 mm hole / 0.254 mm pad+Annular ring: via 0.0762 mm+Copper to board edge: 0.0762 mm+Hole to hole: 0.1524 mm+Board thickness options: 1.6 mm+Copper weight options: 0.5 oz, 1 oz+Surface finishes: ENIG+Max board size: 378.46 x 378.46 mm++Same extended DRC table published for all layer counts; MacroFab supports 2 to 36 layer boards per capabilities page. 2 oz copper requires larger trace, spacing, annular ring and disables the extended option; specific 2 oz numbers not published on the read pages.++Sources:+- https://www.macrofab.com/capabilities/ (read 2026-09-03)+- https://www.macrofab.com/pcba/specs/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0762mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0762mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0762mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0762mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/nextpcb-2L.druadded+71@@ -0,0 +1,71 @@+description[NextPCB 2-layer design rules (standard process) | | Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper | Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper | Min drill: 0.15 mm (5.91 mil) | Min via: 0.2 mm hole / 0.3278 mm pad | Annular ring: via 0.0889 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.3048 mm | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm | Copper weight options: 0.5 oz, 1 oz, 2 oz | Max board size: 1500 x 600 mm | | Trace/spacing table is by copper weight, not layer count: 0.5oz inner 2.5mil width/3mil spacing, 1oz outer 3mil/3mil, 2oz outer 5.5mil/5.5mil. Annular ring: 3.5mil for 1oz, 4.5mil for 2oz. Min drill 0.15mm only for board thickness 1.2mm or less. PTH hole size 0.2mm or larger single side. Copper to V-cut line 0.4mm (15.748mil). Hole to hole different nets 12mil for CAF avoidance; via to via same net 8mil (0.2032mm); PTH to track 9mil (0.2286mm); NPTH to track 8mil (0.2032mm); SMD pad to track 4mil (0.1016mm); SMD pad to SMD pad 0.15mm; pad to pad with hole different nets 0.40mm. Mask sliver (solder bridge dam): green 3.5mil, black/white 5mil (0.127mm), other colors 4mil (0.1016mm). Silk line width: silkscreen printing 5mil (0.127mm), printer printing 3mil (0.0762mm). Finished copper outer 1oz/2oz, inner 0.5oz/1oz/2oz. Surface finish cell left blank on page. BGA 1oz: min pad 0.2mm, min pad distance 0.15mm. Layer count 1 to 32 supported. | | Sources: | - https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.0mil+mdWirePad = 3.0mil+mdWireVia = 3.0mil+mdPadPad = 5.91mil+mdPadVia = 3.0mil+mdViaVia = 3.0mil+mdSmdPad = 3.0mil+mdSmdVia = 3.0mil+mdSmdSmd = 3.0mil+mdCopperDimension = 7.87mil+mdDrill = 12.0mil+msWidth = 2.5mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.5mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.5mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.5mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.5mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/nextpcb-2L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="nextpcb-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0635mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0635mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3048mm" preferredvalue="0.3048mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0762mm"/>+<param name="mdWirePad" value="0.0762mm"/>+<param name="mdWireVia" value="0.0762mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0762mm"/>+<param name="mdViaVia" value="0.0762mm"/>+<param name="mdSmdPad" value="0.0762mm"/>+<param name="mdSmdVia" value="0.0762mm"/>+<param name="mdSmdSmd" value="0.0762mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.3048mm"/>+<param name="msWidth" value="0.0635mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">NextPCB 2-layer design rules (standard process)++Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper+Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper+Min drill: 0.15 mm (5.91 mil)+Min via: 0.2 mm hole / 0.3278 mm pad+Annular ring: via 0.0889 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.3048 mm+Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm+Copper weight options: 0.5 oz, 1 oz, 2 oz+Max board size: 1500 x 600 mm++Trace/spacing table is by copper weight, not layer count: 0.5oz inner 2.5mil width/3mil spacing, 1oz outer 3mil/3mil, 2oz outer 5.5mil/5.5mil. Annular ring: 3.5mil for 1oz, 4.5mil for 2oz. Min drill 0.15mm only for board thickness 1.2mm or less. PTH hole size 0.2mm or larger single side. Copper to V-cut line 0.4mm (15.748mil). Hole to hole different nets 12mil for CAF avoidance; via to via same net 8mil (0.2032mm); PTH to track 9mil (0.2286mm); NPTH to track 8mil (0.2032mm); SMD pad to track 4mil (0.1016mm); SMD pad to SMD pad 0.15mm; pad to pad with hole different nets 0.40mm. Mask sliver (solder bridge dam): green 3.5mil, black/white 5mil (0.127mm), other colors 4mil (0.1016mm). Silk line width: silkscreen printing 5mil (0.127mm), printer printing 3mil (0.0762mm). Finished copper outer 1oz/2oz, inner 0.5oz/1oz/2oz. Surface finish cell left blank on page. BGA 1oz: min pad 0.2mm, min pad distance 0.15mm. Layer count 1 to 32 supported.++Sources:+- https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0889mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0889mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0889mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0889mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/nextpcb-4L.druadded+71@@ -0,0 +1,71 @@+description[NextPCB 4-layer design rules (standard process) | | Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper | Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper | Min drill: 0.15 mm (5.91 mil) | Min via: 0.2 mm hole / 0.3278 mm pad | Annular ring: via 0.0889 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.3048 mm | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm | Copper weight options: 0.5 oz, 1 oz, 2 oz | Max board size: 1500 x 500 mm | | Same published limits as 2 layer except max dimension 1500x500mm for 4 layers. Trace/spacing by copper weight: 0.5oz inner 2.5mil/3mil, 1oz outer 3mil/3mil, 2oz outer 5.5mil/5.5mil. | | Sources: | - https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.0mil+mdWirePad = 3.0mil+mdWireVia = 3.0mil+mdPadPad = 5.91mil+mdPadVia = 3.0mil+mdViaVia = 3.0mil+mdSmdPad = 3.0mil+mdSmdVia = 3.0mil+mdSmdSmd = 3.0mil+mdCopperDimension = 7.87mil+mdDrill = 12.0mil+msWidth = 2.5mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.5mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.5mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.5mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.5mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/nextpcb-4L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="nextpcb-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0635mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0635mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3048mm" preferredvalue="0.3048mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0762mm"/>+<param name="mdWirePad" value="0.0762mm"/>+<param name="mdWireVia" value="0.0762mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0762mm"/>+<param name="mdViaVia" value="0.0762mm"/>+<param name="mdSmdPad" value="0.0762mm"/>+<param name="mdSmdVia" value="0.0762mm"/>+<param name="mdSmdSmd" value="0.0762mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.3048mm"/>+<param name="msWidth" value="0.0635mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">NextPCB 4-layer design rules (standard process)++Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper+Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper+Min drill: 0.15 mm (5.91 mil)+Min via: 0.2 mm hole / 0.3278 mm pad+Annular ring: via 0.0889 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.3048 mm+Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm+Copper weight options: 0.5 oz, 1 oz, 2 oz+Max board size: 1500 x 500 mm++Same published limits as 2 layer except max dimension 1500x500mm for 4 layers. Trace/spacing by copper weight: 0.5oz inner 2.5mil/3mil, 1oz outer 3mil/3mil, 2oz outer 5.5mil/5.5mil.++Sources:+- https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0889mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0889mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0889mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0889mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/nextpcb-6L.druadded+71@@ -0,0 +1,71 @@+description[NextPCB 6-layer design rules (standard process) | | Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper | Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper | Min drill: 0.15 mm (5.91 mil) | Min via: 0.2 mm hole / 0.3278 mm pad | Annular ring: via 0.0889 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.3048 mm | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm | Copper weight options: 0.5 oz, 1 oz, 2 oz | Max board size: 500 x 400 mm | | Max dimension 500x400mm applies to 6 or more layers. Other limits as 2 layer entry. | | Sources: | - https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 3.0mil+mdWirePad = 3.0mil+mdWireVia = 3.0mil+mdPadPad = 5.91mil+mdPadVia = 3.0mil+mdViaVia = 3.0mil+mdSmdPad = 3.0mil+mdSmdVia = 3.0mil+mdSmdSmd = 3.0mil+mdCopperDimension = 7.87mil+mdDrill = 12.0mil+msWidth = 2.5mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.5mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.5mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.5mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.5mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/nextpcb-6L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="nextpcb-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0635mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0635mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0762mm" preferredvalue="0.1524mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3048mm" preferredvalue="0.3048mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0762mm"/>+<param name="mdWirePad" value="0.0762mm"/>+<param name="mdWireVia" value="0.0762mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0762mm"/>+<param name="mdViaVia" value="0.0762mm"/>+<param name="mdSmdPad" value="0.0762mm"/>+<param name="mdSmdVia" value="0.0762mm"/>+<param name="mdSmdSmd" value="0.0762mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.3048mm"/>+<param name="msWidth" value="0.0635mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">NextPCB 6-layer design rules (standard process)++Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper+Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper+Min drill: 0.15 mm (5.91 mil)+Min via: 0.2 mm hole / 0.3278 mm pad+Annular ring: via 0.0889 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.3048 mm+Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm+Copper weight options: 0.5 oz, 1 oz, 2 oz+Max board size: 500 x 400 mm++Max dimension 500x400mm applies to 6 or more layers. Other limits as 2 layer entry.++Sources:+- https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0889mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0889mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0889mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0889mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/nextpcb-advanced-2L.druadded+71@@ -0,0 +1,71 @@+description[NextPCB 2-layer design rules (advanced process) | | Min trace width: 0.0635 mm (2.5 mil) - FR4 complex designs, general advanced | Min spacing: 0.0635 mm (2.5 mil) - FR4 complex designs, general advanced | Min drill: 0.15 mm (5.91 mil) | Min via: 0.075 mm hole | Surface finishes: HASL, Lead Free HASL, ENIG, OSP, Hard Gold, Electrolytic Gold, Gold Fingers, Immersion Tin, Immersion Silver, ENEPIG | Max board size: 500 x 600 mm | | Up to 32 layers, HDI III and any-layer HDI (ELIC). Trace/space by technology: HDI 2.0mil/2.0mil (0.0508mm), heavy copper 3oz 8mil/8mil (0.2032mm), FPC advanced 1.5mil/1.5mil (0.0381mm). Min laser drill microvia 0.075mm, microvia aspect ratio 0.8:1 to 1:1. Min mechanical drill 0.15mm quoted for rigid-flex. Copper up to 10oz outer (heavy copper section) and 4 to 6oz inner; summary banner states up to 6oz outer/4oz inner. Max board size 500x600mm quoted for high-Tg boards. Rigid-flex up to 20 rigid layers plus 8 flex layers. High-speed boards up to 40 layers. Drill aspect ratio up to 20:1. 0.15mm min drill also on rigid-flex section. | | Sources: | - https://www.nextpcb.com/advanced-pcb-manufacturing-capabilities (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 2.5mil+mdWirePad = 2.5mil+mdWireVia = 2.5mil+mdPadPad = 5.91mil+mdPadVia = 2.5mil+mdViaVia = 2.5mil+mdSmdPad = 2.5mil+mdSmdVia = 2.5mil+mdSmdSmd = 2.5mil+mdCopperDimension = 7.87mil+mdDrill = 7.87mil+msWidth = 2.5mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/nextpcb-advanced-2L.edruadded+139@@ -0,0 +1,139 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="nextpcb-advanced-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0635mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0635mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0635mm" preferredvalue="0.127mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0635mm" preferredvalue="0.127mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0635mm" preferredvalue="0.127mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0635mm" preferredvalue="0.127mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0635mm" preferredvalue="0.127mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0635mm" preferredvalue="0.127mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0635mm" preferredvalue="0.127mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0635mm" preferredvalue="0.127mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0635mm"/>+<param name="mdWirePad" value="0.0635mm"/>+<param name="mdWireVia" value="0.0635mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0635mm"/>+<param name="mdViaVia" value="0.0635mm"/>+<param name="mdSmdPad" value="0.0635mm"/>+<param name="mdSmdVia" value="0.0635mm"/>+<param name="mdSmdSmd" value="0.0635mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.0635mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">NextPCB 2-layer design rules (advanced process)++Min trace width: 0.0635 mm (2.5 mil) - FR4 complex designs, general advanced+Min spacing: 0.0635 mm (2.5 mil) - FR4 complex designs, general advanced+Min drill: 0.15 mm (5.91 mil)+Min via: 0.075 mm hole+Surface finishes: HASL, Lead Free HASL, ENIG, OSP, Hard Gold, Electrolytic Gold, Gold Fingers, Immersion Tin, Immersion Silver, ENEPIG+Max board size: 500 x 600 mm++Up to 32 layers, HDI III and any-layer HDI (ELIC). Trace/space by technology: HDI 2.0mil/2.0mil (0.0508mm), heavy copper 3oz 8mil/8mil (0.2032mm), FPC advanced 1.5mil/1.5mil (0.0381mm). Min laser drill microvia 0.075mm, microvia aspect ratio 0.8:1 to 1:1. Min mechanical drill 0.15mm quoted for rigid-flex. Copper up to 10oz outer (heavy copper section) and 4 to 6oz inner; summary banner states up to 6oz outer/4oz inner. Max board size 500x600mm quoted for high-Tg boards. Rigid-flex up to 20 rigid layers plus 8 flex layers. High-speed boards up to 40 layers. Drill aspect ratio up to 20:1. 0.15mm min drill also on rigid-flex section.++Sources:+- https://www.nextpcb.com/advanced-pcb-manufacturing-capabilities (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/osh-park-2L.druadded+71@@ -0,0 +1,71 @@+description[OSH Park 2-layer design rules (standard process) | | Min trace width: 0.1524 mm (6.0 mil) - 1oz copper | Min spacing: 0.1524 mm (6.0 mil) - 1oz copper | Min drill: 0.254 mm (10.0 mil) | Min via: 0.254 mm hole / 0.508 mm pad | Annular ring: via 0.127 mm | Copper to board edge: 0.381 mm | Hole to hole: 0.127 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz | Surface finishes: ENIG | Max board size: 406.4 x 558.8 mm | | Soldermask SMOBC purple both sides. Maximum soldermask alignment 3 mil (0.0762mm) covering retraction, expansion, and shift. Minimum board size 0.25in (6.35mm) square. Maximum soldermask web 4 mil is the minimum web, listed under maskSliver. Substrate 175Tg FR4. Via pad diameter not published. Minimum slot size 20 mil (0.508mm) drill slot only. Blind, buried, and filled+plated vias not supported. | | Sources: | - https://docs.oshpark.com/services/two-layer/ (read 2026-09-03) | - https://docs.oshpark.com/services/ (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 6.0mil+mdWirePad = 6.0mil+mdWireVia = 6.0mil+mdPadPad = 6.0mil+mdPadVia = 6.0mil+mdViaVia = 6.0mil+mdSmdPad = 6.0mil+mdSmdVia = 6.0mil+mdSmdSmd = 6.0mil+mdCopperDimension = 15.0mil+mdDrill = 5.0mil+msWidth = 6.0mil+msDrill = 10.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/osh-park-2L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="osh-park-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1524mm" preferredvalue="0.4572mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1524mm" preferredvalue="0.3048mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.254mm" preferredvalue="0.508mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.254mm" preferredvalue="0.508mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.381mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.127mm" preferredvalue="0.127mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1524mm"/>+<param name="mdWirePad" value="0.1524mm"/>+<param name="mdWireVia" value="0.1524mm"/>+<param name="mdPadPad" value="0.1524mm"/>+<param name="mdPadVia" value="0.1524mm"/>+<param name="mdViaVia" value="0.1524mm"/>+<param name="mdSmdPad" value="0.1524mm"/>+<param name="mdSmdVia" value="0.1524mm"/>+<param name="mdSmdSmd" value="0.1524mm"/>+<param name="mdCopperDimension" value="0.381mm"/>+<param name="mdDrill" value="0.127mm"/>+<param name="msWidth" value="0.1524mm"/>+<param name="msDrill" value="0.254mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">OSH Park 2-layer design rules (standard process)++Min trace width: 0.1524 mm (6.0 mil) - 1oz copper+Min spacing: 0.1524 mm (6.0 mil) - 1oz copper+Min drill: 0.254 mm (10.0 mil)+Min via: 0.254 mm hole / 0.508 mm pad+Annular ring: via 0.127 mm+Copper to board edge: 0.381 mm+Hole to hole: 0.127 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz+Surface finishes: ENIG+Max board size: 406.4 x 558.8 mm++Soldermask SMOBC purple both sides. Maximum soldermask alignment 3 mil (0.0762mm) covering retraction, expansion, and shift. Minimum board size 0.25in (6.35mm) square. Maximum soldermask web 4 mil is the minimum web, listed under maskSliver. Substrate 175Tg FR4. Via pad diameter not published. Minimum slot size 20 mil (0.508mm) drill slot only. Blind, buried, and filled+plated vias not supported.++Sources:+- https://docs.oshpark.com/services/two-layer/ (read 2026-09-03)+- https://docs.oshpark.com/services/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.127mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.127mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.127mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.127mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/osh-park-2oz-0.8mm-2L.druadded+71@@ -0,0 +1,71 @@+description[OSH Park 2-layer design rules (2oz-0.8mm process) | | Min trace width: 0.1524 mm (6.0 mil) - 2oz copper | Min spacing: 0.1524 mm (6.0 mil) - 2oz copper | Min drill: 0.254 mm (10.0 mil) | Min via: 0.254 mm hole / 0.508 mm pad | Annular ring: via 0.127 mm | Copper to board edge: 0.381 mm | Hole to hole: 0.127 mm | Board thickness options: 0.8 mm | Copper weight options: 2 oz | Surface finishes: ENIG | Max board size: 406.4 x 558.8 mm | | 0.032in (0.8mm) thick PCB with 2oz (2.8 mil, 70um) copper, 180Tg FR4 (Ventec VT-47). Minimum board size 0.25in (6.35mm) square. | | Sources: | - https://docs.oshpark.com/services/two-layer-hhdc/ (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 6.0mil+mdWirePad = 6.0mil+mdWireVia = 6.0mil+mdPadPad = 6.0mil+mdPadVia = 6.0mil+mdViaVia = 6.0mil+mdSmdPad = 6.0mil+mdSmdVia = 6.0mil+mdSmdSmd = 6.0mil+mdCopperDimension = 15.0mil+mdDrill = 5.0mil+msWidth = 6.0mil+msDrill = 10.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/osh-park-2oz-0.8mm-2L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="osh-park-2oz-0.8mm-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1524mm" preferredvalue="0.4572mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1524mm" preferredvalue="0.3048mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.254mm" preferredvalue="0.508mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.254mm" preferredvalue="0.508mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.381mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.127mm" preferredvalue="0.127mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1524mm"/>+<param name="mdWirePad" value="0.1524mm"/>+<param name="mdWireVia" value="0.1524mm"/>+<param name="mdPadPad" value="0.1524mm"/>+<param name="mdPadVia" value="0.1524mm"/>+<param name="mdViaVia" value="0.1524mm"/>+<param name="mdSmdPad" value="0.1524mm"/>+<param name="mdSmdVia" value="0.1524mm"/>+<param name="mdSmdSmd" value="0.1524mm"/>+<param name="mdCopperDimension" value="0.381mm"/>+<param name="mdDrill" value="0.127mm"/>+<param name="msWidth" value="0.1524mm"/>+<param name="msDrill" value="0.254mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">OSH Park 2-layer design rules (2oz-0.8mm process)++Min trace width: 0.1524 mm (6.0 mil) - 2oz copper+Min spacing: 0.1524 mm (6.0 mil) - 2oz copper+Min drill: 0.254 mm (10.0 mil)+Min via: 0.254 mm hole / 0.508 mm pad+Annular ring: via 0.127 mm+Copper to board edge: 0.381 mm+Hole to hole: 0.127 mm+Board thickness options: 0.8 mm+Copper weight options: 2 oz+Surface finishes: ENIG+Max board size: 406.4 x 558.8 mm++0.032in (0.8mm) thick PCB with 2oz (2.8 mil, 70um) copper, 180Tg FR4 (Ventec VT-47). Minimum board size 0.25in (6.35mm) square.++Sources:+- https://docs.oshpark.com/services/two-layer-hhdc/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.127mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.127mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.127mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.127mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/osh-park-4L.druadded+71@@ -0,0 +1,71 @@+description[OSH Park 4-layer design rules (standard process) | | Min trace width: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper | Min spacing: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper | Min drill: 0.254 mm (10.0 mil) | Min via: 0.254 mm hole / 0.4572 mm pad | Annular ring: via 0.1016 mm | Copper to board edge: 0.381 mm | Hole to hole: 0.127 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz | Surface finishes: ENIG | Max board size: 406.4 x 558.8 mm | | Copper weight is 1oz outer, 0.5oz inner. Plated drill to internal layer copper clearance 10 mil (0.254mm). Substrate 190Tg FR408-HR. Blind and buried vias not supported. Minimum board size 0.25in (6.35mm) square. Via pad diameter not published. | | Sources: | - https://docs.oshpark.com/services/four-layer/ (read 2026-09-03) | - https://docs.oshpark.com/services/ (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 15.0mil+mdDrill = 5.0mil+msWidth = 5.0mil+msDrill = 10.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/osh-park-4L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="osh-park-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.127mm" preferredvalue="0.381mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.127mm" preferredvalue="0.254mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.254mm" preferredvalue="0.508mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.254mm" preferredvalue="0.508mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.381mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.127mm" preferredvalue="0.127mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.381mm"/>+<param name="mdDrill" value="0.127mm"/>+<param name="msWidth" value="0.127mm"/>+<param name="msDrill" value="0.254mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">OSH Park 4-layer design rules (standard process)++Min trace width: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper+Min spacing: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper+Min drill: 0.254 mm (10.0 mil)+Min via: 0.254 mm hole / 0.4572 mm pad+Annular ring: via 0.1016 mm+Copper to board edge: 0.381 mm+Hole to hole: 0.127 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz+Surface finishes: ENIG+Max board size: 406.4 x 558.8 mm++Copper weight is 1oz outer, 0.5oz inner. Plated drill to internal layer copper clearance 10 mil (0.254mm). Substrate 190Tg FR408-HR. Blind and buried vias not supported. Minimum board size 0.25in (6.35mm) square. Via pad diameter not published.++Sources:+- https://docs.oshpark.com/services/four-layer/ (read 2026-09-03)+- https://docs.oshpark.com/services/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1016mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1016mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1016mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1016mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/osh-park-6L.druadded+71@@ -0,0 +1,71 @@+description[OSH Park 6-layer design rules (standard process) | | Min trace width: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper | Min spacing: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper | Min drill: 0.2032 mm (8.0 mil) | Min via: 0.2032 mm hole / 0.4064 mm pad | Annular ring: via 0.1016 mm | Copper to board edge: 0.381 mm | Hole to hole: 0.127 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz | Surface finishes: ENIG | Max board size: 406.4 x 558.8 mm | | Summary values from the services index page. Blind and buried vias not supported. | | Sources: | - https://docs.oshpark.com/services/ (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 15.0mil+mdDrill = 5.0mil+msWidth = 5.0mil+msDrill = 8.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/osh-park-6L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="osh-park-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.127mm" preferredvalue="0.381mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.127mm" preferredvalue="0.254mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.2032mm" preferredvalue="0.4064mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.2032mm" preferredvalue="0.4064mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.381mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.127mm" preferredvalue="0.127mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.381mm"/>+<param name="mdDrill" value="0.127mm"/>+<param name="msWidth" value="0.127mm"/>+<param name="msDrill" value="0.2032mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">OSH Park 6-layer design rules (standard process)++Min trace width: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper+Min spacing: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper+Min drill: 0.2032 mm (8.0 mil)+Min via: 0.2032 mm hole / 0.4064 mm pad+Annular ring: via 0.1016 mm+Copper to board edge: 0.381 mm+Hole to hole: 0.127 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz+Surface finishes: ENIG+Max board size: 406.4 x 558.8 mm++Summary values from the services index page. Blind and buried vias not supported.++Sources:+- https://docs.oshpark.com/services/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1016mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1016mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1016mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1016mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/osh-park-after-dark-2L.druadded+71@@ -0,0 +1,71 @@+description[OSH Park 2-layer design rules (after-dark process) | | Min trace width: 0.1524 mm (6.0 mil) - 1oz copper | Min spacing: 0.1524 mm (6.0 mil) - 1oz copper | Min drill: 0.254 mm (10.0 mil) | Min via: 0.254 mm hole / 0.508 mm pad | Annular ring: via 0.127 mm | Copper to board edge: 0.381 mm | Hole to hole: 0.127 mm | Board thickness options: 1.6 mm | Copper weight options: 1 oz | Surface finishes: ENIG | Max board size: 406.4 x 558.8 mm | | Clear soldermask on black 180Tg FR4 (Ventec VT 447 b), opaque light blocking. Same copper and drill rules as standard 2 layer. Minimum board size 0.25in (6.35mm) square. | | Sources: | - https://docs.oshpark.com/services/afterdark/ (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 6.0mil+mdWirePad = 6.0mil+mdWireVia = 6.0mil+mdPadPad = 6.0mil+mdPadVia = 6.0mil+mdViaVia = 6.0mil+mdSmdPad = 6.0mil+mdSmdVia = 6.0mil+mdSmdSmd = 6.0mil+mdCopperDimension = 15.0mil+mdDrill = 5.0mil+msWidth = 6.0mil+msDrill = 10.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/osh-park-after-dark-2L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="osh-park-after-dark-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1524mm" preferredvalue="0.4572mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1524mm" preferredvalue="0.3048mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.254mm" preferredvalue="0.508mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.254mm" preferredvalue="0.508mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.381mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.127mm" preferredvalue="0.127mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1524mm"/>+<param name="mdWirePad" value="0.1524mm"/>+<param name="mdWireVia" value="0.1524mm"/>+<param name="mdPadPad" value="0.1524mm"/>+<param name="mdPadVia" value="0.1524mm"/>+<param name="mdViaVia" value="0.1524mm"/>+<param name="mdSmdPad" value="0.1524mm"/>+<param name="mdSmdVia" value="0.1524mm"/>+<param name="mdSmdSmd" value="0.1524mm"/>+<param name="mdCopperDimension" value="0.381mm"/>+<param name="mdDrill" value="0.127mm"/>+<param name="msWidth" value="0.1524mm"/>+<param name="msDrill" value="0.254mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">OSH Park 2-layer design rules (after-dark process)++Min trace width: 0.1524 mm (6.0 mil) - 1oz copper+Min spacing: 0.1524 mm (6.0 mil) - 1oz copper+Min drill: 0.254 mm (10.0 mil)+Min via: 0.254 mm hole / 0.508 mm pad+Annular ring: via 0.127 mm+Copper to board edge: 0.381 mm+Hole to hole: 0.127 mm+Board thickness options: 1.6 mm+Copper weight options: 1 oz+Surface finishes: ENIG+Max board size: 406.4 x 558.8 mm++Clear soldermask on black 180Tg FR4 (Ventec VT 447 b), opaque light blocking. Same copper and drill rules as standard 2 layer. Minimum board size 0.25in (6.35mm) square.++Sources:+- https://docs.oshpark.com/services/afterdark/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.127mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.127mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.127mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.127mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/osh-park-flex-2L.druadded+71@@ -0,0 +1,71 @@+description[OSH Park 2-layer design rules (flex process) | | Min trace width: 0.1524 mm (6.0 mil) - 1oz copper | Min spacing: 0.1524 mm (6.0 mil) - 1oz copper | Min drill: 0.254 mm (10.0 mil) | Min via: 0.254 mm hole / 0.508 mm pad | Annular ring: via 0.127 mm | Copper to board edge: 0.1524 mm | Hole to hole: 0.127 mm | Board thickness options: 0.1016 mm | Copper weight options: 1 oz | Surface finishes: ENIG | Max board size: 406.4 x 254 mm | | Service temporarily suspended. Panasonic Felios polyimide, 4 mil (0.1016mm) core, clear soldermask. Recommended minimum flex strip width 250 mil (6.35mm). Minimum board size 0.25in (6.35mm) square. | | Sources: | - https://docs.oshpark.com/services/flex/ (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 6.0mil+mdWirePad = 6.0mil+mdWireVia = 6.0mil+mdPadPad = 6.0mil+mdPadVia = 6.0mil+mdViaVia = 6.0mil+mdSmdPad = 6.0mil+mdSmdVia = 6.0mil+mdSmdSmd = 6.0mil+mdCopperDimension = 6.0mil+mdDrill = 5.0mil+msWidth = 6.0mil+msDrill = 10.0mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/osh-park-flex-2L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="osh-park-flex-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1524mm" preferredvalue="0.4572mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1524mm" preferredvalue="0.3048mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.254mm" preferredvalue="0.508mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.254mm" preferredvalue="0.508mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.1524mm" preferredvalue="0.1524mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1524mm" preferredvalue="0.3048mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.1524mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.127mm" preferredvalue="0.127mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1524mm"/>+<param name="mdWirePad" value="0.1524mm"/>+<param name="mdWireVia" value="0.1524mm"/>+<param name="mdPadPad" value="0.1524mm"/>+<param name="mdPadVia" value="0.1524mm"/>+<param name="mdViaVia" value="0.1524mm"/>+<param name="mdSmdPad" value="0.1524mm"/>+<param name="mdSmdVia" value="0.1524mm"/>+<param name="mdSmdSmd" value="0.1524mm"/>+<param name="mdCopperDimension" value="0.1524mm"/>+<param name="mdDrill" value="0.127mm"/>+<param name="msWidth" value="0.1524mm"/>+<param name="msDrill" value="0.254mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">OSH Park 2-layer design rules (flex process)++Min trace width: 0.1524 mm (6.0 mil) - 1oz copper+Min spacing: 0.1524 mm (6.0 mil) - 1oz copper+Min drill: 0.254 mm (10.0 mil)+Min via: 0.254 mm hole / 0.508 mm pad+Annular ring: via 0.127 mm+Copper to board edge: 0.1524 mm+Hole to hole: 0.127 mm+Board thickness options: 0.1016 mm+Copper weight options: 1 oz+Surface finishes: ENIG+Max board size: 406.4 x 254 mm++Service temporarily suspended. Panasonic Felios polyimide, 4 mil (0.1016mm) core, clear soldermask. Recommended minimum flex strip width 250 mil (6.35mm). Minimum board size 0.25in (6.35mm) square.++Sources:+- https://docs.oshpark.com/services/flex/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.127mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.127mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.127mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.127mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/pcbway-2L.druadded+71@@ -0,0 +1,71 @@+description[PCBWay 2-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - prototype process, any copper weight; per copper weight outer layer limits are 0.5oz: 4/5mil, 1oz: 5/6mil, 2oz: 7/8mil, 3oz: 10/12mil (before compensation) | Min spacing: 0.1016 mm (4.0 mil) - prototype process, different nets; per copper weight outer layer limits are 0.5oz: 4/5mil, 1oz: 5/6mil, 2oz: 7/8mil, 3oz: 10/12mil (before compensation) | Min drill: 0.2 mm (7.87 mil) | Min via: 0.2 mm hole / 0.454 mm pad | Annular ring: via 0.127 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.2794 mm | Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm | Copper weight options: 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz | Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin | Max board size: 508 x 610 mm | | Min board thickness 0.3mm, max board thickness 3.2mm. Prototype quote page lists max PCB size 500x1100mm and drill range 0.2 to 6.3mm. Grid trace 1oz: 9/11mil. Hole diameter tolerance PTH: plus or minus 0.075mm. Panel size max 20x24 inch. | | Sources: | - https://www.pcbway.com/capabilities.html (read 2026-09-03) | - https://m.pcbway.com/capabilities.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 9.84mil+mdDrill = 11.0mil+msWidth = 4.0mil+msDrill = 7.87mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/pcbway-2L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="pcbway-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.2mm" preferredvalue="0.4mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.2mm" preferredvalue="0.4mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2794mm" preferredvalue="0.2794mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.25mm"/>+<param name="mdDrill" value="0.2794mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.2mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">PCBWay 2-layer design rules (standard process)++Min trace width: 0.1016 mm (4.0 mil) - prototype process, any copper weight; per copper weight outer layer limits are 0.5oz: 4/5mil, 1oz: 5/6mil, 2oz: 7/8mil, 3oz: 10/12mil (before compensation)+Min spacing: 0.1016 mm (4.0 mil) - prototype process, different nets; per copper weight outer layer limits are 0.5oz: 4/5mil, 1oz: 5/6mil, 2oz: 7/8mil, 3oz: 10/12mil (before compensation)+Min drill: 0.2 mm (7.87 mil)+Min via: 0.2 mm hole / 0.454 mm pad+Annular ring: via 0.127 mm+Copper to board edge: 0.25 mm+Hole to hole: 0.2794 mm+Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+Copper weight options: 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin+Max board size: 508 x 610 mm++Min board thickness 0.3mm, max board thickness 3.2mm. Prototype quote page lists max PCB size 500x1100mm and drill range 0.2 to 6.3mm. Grid trace 1oz: 9/11mil. Hole diameter tolerance PTH: plus or minus 0.075mm. Panel size max 20x24 inch.++Sources:+- https://www.pcbway.com/capabilities.html (read 2026-09-03)+- https://m.pcbway.com/capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.127mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.127mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.127mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.127mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/pcbway-4L.druadded+71@@ -0,0 +1,71 @@+description[PCBWay 4-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 0.5oz: 4mil, 2oz: 6mil, 3oz: 8mil. Outer layer 1oz: 5mil | Min spacing: 0.127 mm (5.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 0.5oz: 5mil (4/4mil class), 2oz: 8mil, 3oz: 11mil. Outer layer 1oz: 6mil | Min drill: 0.2 mm (7.87 mil) | Min via: 0.2 mm hole / 0.454 mm pad | Annular ring: via 0.127 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.2794 mm | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm | Copper weight options: 0.5 oz, 1 oz, 1.5 oz, 2 oz, 3 oz, 4 oz | Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin | Max board size: 508 x 600 mm | | Min board thickness 0.6mm, max board thickness 3.2mm. Min inner layer isolation ring (hole to inner layer conductor, before compensation) 7mil (0.1778mm). Inner layer copper weight options 1oz or 1.5oz. Max aspect ratio 8:1. | | Sources: | - https://www.pcbway.com/capabilities.html (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 9.84mil+mdDrill = 11.0mil+msWidth = 4.0mil+msDrill = 7.87mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/pcbway-4L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="pcbway-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.2mm" preferredvalue="0.4mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.2mm" preferredvalue="0.4mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2794mm" preferredvalue="0.2794mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.25mm"/>+<param name="mdDrill" value="0.2794mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.2mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">PCBWay 4-layer design rules (standard process)++Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 0.5oz: 4mil, 2oz: 6mil, 3oz: 8mil. Outer layer 1oz: 5mil+Min spacing: 0.127 mm (5.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 0.5oz: 5mil (4/4mil class), 2oz: 8mil, 3oz: 11mil. Outer layer 1oz: 6mil+Min drill: 0.2 mm (7.87 mil)+Min via: 0.2 mm hole / 0.454 mm pad+Annular ring: via 0.127 mm+Copper to board edge: 0.25 mm+Hole to hole: 0.2794 mm+Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+Copper weight options: 0.5 oz, 1 oz, 1.5 oz, 2 oz, 3 oz, 4 oz+Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin+Max board size: 508 x 600 mm++Min board thickness 0.6mm, max board thickness 3.2mm. Min inner layer isolation ring (hole to inner layer conductor, before compensation) 7mil (0.1778mm). Inner layer copper weight options 1oz or 1.5oz. Max aspect ratio 8:1.++Sources:+- https://www.pcbway.com/capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.127mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.127mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.127mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.127mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/pcbway-6L.druadded+71@@ -0,0 +1,71 @@+description[PCBWay 6-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1oz (35um) copper, before compensation; outer layer 1oz: 5mil | Min spacing: 0.127 mm (5.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 2oz: 8mil, 3oz: 11mil. Outer layer 1oz: 6mil | Min drill: 0.2 mm (7.87 mil) | Min via: 0.2 mm hole / 0.454 mm pad | Annular ring: via 0.127 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.2794 mm | Board thickness options: 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm | Copper weight options: 0.5 oz, 1 oz, 1.5 oz, 2 oz, 3 oz, 4 oz | Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin | Max board size: 508 x 600 mm | | Min board thickness 0.9mm, max board thickness 3.2mm. Min inner layer isolation ring (hole to inner layer conductor, before compensation) 8mil (0.2032mm). Inner layer copper weight options 1oz or 1.5oz. Max aspect ratio 8:1. | | Sources: | - https://www.pcbway.com/capabilities.html (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 9.84mil+mdDrill = 11.0mil+msWidth = 4.0mil+msDrill = 7.87mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 5.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 5.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 5.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 5.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/pcbway-6L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="pcbway-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.2mm" preferredvalue="0.4mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.2mm" preferredvalue="0.4mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.25mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2794mm" preferredvalue="0.2794mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.25mm"/>+<param name="mdDrill" value="0.2794mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.2mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">PCBWay 6-layer design rules (standard process)++Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1oz (35um) copper, before compensation; outer layer 1oz: 5mil+Min spacing: 0.127 mm (5.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 2oz: 8mil, 3oz: 11mil. Outer layer 1oz: 6mil+Min drill: 0.2 mm (7.87 mil)+Min via: 0.2 mm hole / 0.454 mm pad+Annular ring: via 0.127 mm+Copper to board edge: 0.25 mm+Hole to hole: 0.2794 mm+Board thickness options: 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+Copper weight options: 0.5 oz, 1 oz, 1.5 oz, 2 oz, 3 oz, 4 oz+Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin+Max board size: 508 x 600 mm++Min board thickness 0.9mm, max board thickness 3.2mm. Min inner layer isolation ring (hole to inner layer conductor, before compensation) 8mil (0.2032mm). Inner layer copper weight options 1oz or 1.5oz. Max aspect ratio 8:1.++Sources:+- https://www.pcbway.com/capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.127mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.127mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.127mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.127mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/pcbway-advanced-2L.druadded+71@@ -0,0 +1,71 @@+description[PCBWay 2-layer design rules (advanced process) | | Min trace width: 0.0508 mm (2.0 mil) - outer layer, 1/3 oz base copper, only part of traces on the board, not whole board; capabilities table advanced outer 0.5oz: 4mil with parts 3.5mil (0.0889mm) in BGA chip area | Min spacing: 0.0508 mm (2.0 mil) - outer layer, 1/3 oz base copper, partial traces only; capabilities table advanced outer 0.5oz: 4mil, parts 3.5mil | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.3024 mm pad | Annular ring: via 0.0762 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.3556 mm | Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm | Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz | Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver | Max board size: 609 x 889 mm | | Advanced page does not distinguish limits by layer count for 2 layers. Min board thickness 0.25mm. Max aspect ratio 20:1. Max layer count 64. Min BGA pad diameter 8mil, min BGA pitch 0.4mm. Min base copper 1/3 oz, max finished copper 8 oz. Min insulating layer thickness 2mil. Max board thickness 4.5mm. | | Sources: | - https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03) | - https://www.pcbway.com/capabilities.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 2.0mil+mdWirePad = 2.0mil+mdWireVia = 2.0mil+mdPadPad = 5.91mil+mdPadVia = 2.0mil+mdViaVia = 2.0mil+mdSmdPad = 2.0mil+mdSmdVia = 2.0mil+mdSmdSmd = 2.0mil+mdCopperDimension = 7.87mil+mdDrill = 14.0mil+msWidth = 2.0mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/pcbway-advanced-2L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="pcbway-advanced-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0508mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0508mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3556mm" preferredvalue="0.3556mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0508mm"/>+<param name="mdWirePad" value="0.0508mm"/>+<param name="mdWireVia" value="0.0508mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0508mm"/>+<param name="mdViaVia" value="0.0508mm"/>+<param name="mdSmdPad" value="0.0508mm"/>+<param name="mdSmdVia" value="0.0508mm"/>+<param name="mdSmdSmd" value="0.0508mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.3556mm"/>+<param name="msWidth" value="0.0508mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">PCBWay 2-layer design rules (advanced process)++Min trace width: 0.0508 mm (2.0 mil) - outer layer, 1/3 oz base copper, only part of traces on the board, not whole board; capabilities table advanced outer 0.5oz: 4mil with parts 3.5mil (0.0889mm) in BGA chip area+Min spacing: 0.0508 mm (2.0 mil) - outer layer, 1/3 oz base copper, partial traces only; capabilities table advanced outer 0.5oz: 4mil, parts 3.5mil+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.3024 mm pad+Annular ring: via 0.0762 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.3556 mm+Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz+Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver+Max board size: 609 x 889 mm++Advanced page does not distinguish limits by layer count for 2 layers. Min board thickness 0.25mm. Max aspect ratio 20:1. Max layer count 64. Min BGA pad diameter 8mil, min BGA pitch 0.4mm. Min base copper 1/3 oz, max finished copper 8 oz. Min insulating layer thickness 2mil. Max board thickness 4.5mm.++Sources:+- https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03)+- https://www.pcbway.com/capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0762mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0762mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0762mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0762mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/pcbway-advanced-4L.druadded+71@@ -0,0 +1,71 @@+description[PCBWay 4-layer design rules (advanced process) | | Min trace width: 0.0508 mm (2.0 mil) - inner layer 2/2mil with H/H oz base copper (partial traces only); capabilities table advanced inner 0.5oz: 4mil, parts 3.5mil. Outer layer 2/2mil with 1/3 oz base copper | Min spacing: 0.0508 mm (2.0 mil) - inner layer H/H oz or outer 1/3 oz base copper, partial traces only; capabilities table advanced inner 0.5oz: 3.5mil spacing (4/3.5mil), outer 0.5oz: 4mil | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.3024 mm pad | Annular ring: via 0.0762 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.3556 mm | Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm | Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz | Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver | Max board size: 609 x 889 mm | | Advanced page does not distinguish limits by layer count; same published values apply to 4 layers. Min board thickness 0.4mm (advanced), standard 0.6mm. Min inner layer isolation ring advanced 6mil (0.1524mm) before compensation. Max aspect ratio 20:1. HDI 1 to 7 steps. Max board thickness 4.5mm. | | Sources: | - https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03) | - https://www.pcbway.com/capabilities.html (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 2.0mil+mdWirePad = 2.0mil+mdWireVia = 2.0mil+mdPadPad = 5.91mil+mdPadVia = 2.0mil+mdViaVia = 2.0mil+mdSmdPad = 2.0mil+mdSmdVia = 2.0mil+mdSmdSmd = 2.0mil+mdCopperDimension = 7.87mil+mdDrill = 14.0mil+msWidth = 2.0mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/pcbway-advanced-4L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="pcbway-advanced-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0508mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0508mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3556mm" preferredvalue="0.3556mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0508mm"/>+<param name="mdWirePad" value="0.0508mm"/>+<param name="mdWireVia" value="0.0508mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0508mm"/>+<param name="mdViaVia" value="0.0508mm"/>+<param name="mdSmdPad" value="0.0508mm"/>+<param name="mdSmdVia" value="0.0508mm"/>+<param name="mdSmdSmd" value="0.0508mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.3556mm"/>+<param name="msWidth" value="0.0508mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">PCBWay 4-layer design rules (advanced process)++Min trace width: 0.0508 mm (2.0 mil) - inner layer 2/2mil with H/H oz base copper (partial traces only); capabilities table advanced inner 0.5oz: 4mil, parts 3.5mil. Outer layer 2/2mil with 1/3 oz base copper+Min spacing: 0.0508 mm (2.0 mil) - inner layer H/H oz or outer 1/3 oz base copper, partial traces only; capabilities table advanced inner 0.5oz: 3.5mil spacing (4/3.5mil), outer 0.5oz: 4mil+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.3024 mm pad+Annular ring: via 0.0762 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.3556 mm+Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz+Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver+Max board size: 609 x 889 mm++Advanced page does not distinguish limits by layer count; same published values apply to 4 layers. Min board thickness 0.4mm (advanced), standard 0.6mm. Min inner layer isolation ring advanced 6mil (0.1524mm) before compensation. Max aspect ratio 20:1. HDI 1 to 7 steps. Max board thickness 4.5mm.++Sources:+- https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03)+- https://www.pcbway.com/capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0762mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0762mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0762mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0762mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/pcbway-advanced-6L.druadded+71@@ -0,0 +1,71 @@+description[PCBWay 6-layer design rules (advanced process) | | Min trace width: 0.0508 mm (2.0 mil) - inner layer 2/2mil with H/H oz base copper (partial traces only); capabilities table advanced inner 0.5oz: 4mil, parts 3.5mil. Outer layer 2/2mil with 1/3 oz base copper | Min spacing: 0.0508 mm (2.0 mil) - inner layer H/H oz or outer 1/3 oz base copper, partial traces only; capabilities table advanced inner 0.5oz: 3.5mil spacing, outer 0.5oz: 4mil | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.3024 mm pad | Annular ring: via 0.0762 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.3556 mm | Board thickness options: 0.7 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm | Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz | Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver | Max board size: 609 x 889 mm | | Advanced page does not distinguish limits by layer count; same published values apply to 6 layers. Min board thickness 0.7mm (advanced), standard 0.9mm. Min inner layer isolation ring advanced 6.5mil (0.1651mm) before compensation. Max aspect ratio 20:1. HDI 1 to 7 steps. Max board thickness 4.5mm. | | Sources: | - https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03) | - https://www.pcbway.com/capabilities.html (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 2.0mil+mdWirePad = 2.0mil+mdWireVia = 2.0mil+mdPadPad = 5.91mil+mdPadVia = 2.0mil+mdViaVia = 2.0mil+mdSmdPad = 2.0mil+mdSmdVia = 2.0mil+mdSmdSmd = 2.0mil+mdCopperDimension = 7.87mil+mdDrill = 14.0mil+msWidth = 2.0mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/pcbway-advanced-6L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="pcbway-advanced-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.0508mm" preferredvalue="0.3mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.0508mm" preferredvalue="0.2mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.0508mm" preferredvalue="0.1016mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3556mm" preferredvalue="0.3556mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.0508mm"/>+<param name="mdWirePad" value="0.0508mm"/>+<param name="mdWireVia" value="0.0508mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.0508mm"/>+<param name="mdViaVia" value="0.0508mm"/>+<param name="mdSmdPad" value="0.0508mm"/>+<param name="mdSmdVia" value="0.0508mm"/>+<param name="mdSmdSmd" value="0.0508mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.3556mm"/>+<param name="msWidth" value="0.0508mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">PCBWay 6-layer design rules (advanced process)++Min trace width: 0.0508 mm (2.0 mil) - inner layer 2/2mil with H/H oz base copper (partial traces only); capabilities table advanced inner 0.5oz: 4mil, parts 3.5mil. Outer layer 2/2mil with 1/3 oz base copper+Min spacing: 0.0508 mm (2.0 mil) - inner layer H/H oz or outer 1/3 oz base copper, partial traces only; capabilities table advanced inner 0.5oz: 3.5mil spacing, outer 0.5oz: 4mil+Min drill: 0.15 mm (5.91 mil)+Min via: 0.15 mm hole / 0.3024 mm pad+Annular ring: via 0.0762 mm+Copper to board edge: 0.2 mm+Hole to hole: 0.3556 mm+Board thickness options: 0.7 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz+Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver+Max board size: 609 x 889 mm++Advanced page does not distinguish limits by layer count; same published values apply to 6 layers. Min board thickness 0.7mm (advanced), standard 0.9mm. Min inner layer isolation ring advanced 6.5mil (0.1651mm) before compensation. Max aspect ratio 20:1. HDI 1 to 7 steps. Max board thickness 4.5mm.++Sources:+- https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03)+- https://www.pcbway.com/capabilities.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0762mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0762mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0762mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0762mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/seeed-fusion-2L.druadded+71@@ -0,0 +1,71 @@+description[Seeed Fusion 2-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - 1 oz copper, 4/4 mil option | Min spacing: 0.1016 mm (4.0 mil) - 1 oz copper, 4/4 mil option | Min drill: 0.2 mm (7.87 mil) | Min via: 0.2 mm hole / 0.4 mm pad | Annular ring: via 0.1 mm | Copper to board edge: 0.3 mm | Hole to hole: 0.3 mm | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm | Copper weight options: 1 oz, 2 oz, 3 oz | Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold | Max board size: 500 x 500 mm | | Trace width/spacing by copper weight: 1 oz: 4/4, 5/5, or 6/6 mil options (0.1016/0.127/0.1524 mm); 2 oz: 10/10 mil (0.254 mm); 3 oz: 15/15 mil (0.381 mm). RF coil designs require 6/6 mil but select 4/4 mil option. Min board size 10 x 10 mm. Drill ranges: NPTH 0.2 to 6.3 mm, PTH 0.2 to 5.8 mm, via holes 0.2 to 0.5 mm (vias 0.3 mm and smaller guarantee full mask tenting). Min via pad not published directly, min annular ring 0.1 mm implies pad = drill + 0.2 mm. Min plated slot 0.65 mm, non-plated slot 0.8 mm. BGA pitch guidance: 0.45 mm pitch with 6/6 mil, 0.35 mm with 5/5 mil, 0.25 mm with 4/4 mil. | | Sources: | - https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03) | - https://www.seeedstudio.com/fusion_pcb.html (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 11.81mil+mdDrill = 11.81mil+msWidth = 4.0mil+msDrill = 7.87mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/seeed-fusion-2L.edruadded+145@@ -0,0 +1,145 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="seeed-fusion-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.2mm" preferredvalue="0.4mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.2mm" preferredvalue="0.4mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.3mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.3mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.2mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Seeed Fusion 2-layer design rules (standard process)++Min trace width: 0.1016 mm (4.0 mil) - 1 oz copper, 4/4 mil option+Min spacing: 0.1016 mm (4.0 mil) - 1 oz copper, 4/4 mil option+Min drill: 0.2 mm (7.87 mil)+Min via: 0.2 mm hole / 0.4 mm pad+Annular ring: via 0.1 mm+Copper to board edge: 0.3 mm+Hole to hole: 0.3 mm+Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm+Copper weight options: 1 oz, 2 oz, 3 oz+Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold+Max board size: 500 x 500 mm++Trace width/spacing by copper weight: 1 oz: 4/4, 5/5, or 6/6 mil options (0.1016/0.127/0.1524 mm); 2 oz: 10/10 mil (0.254 mm); 3 oz: 15/15 mil (0.381 mm). RF coil designs require 6/6 mil but select 4/4 mil option. Min board size 10 x 10 mm. Drill ranges: NPTH 0.2 to 6.3 mm, PTH 0.2 to 5.8 mm, via holes 0.2 to 0.5 mm (vias 0.3 mm and smaller guarantee full mask tenting). Min via pad not published directly, min annular ring 0.1 mm implies pad = drill + 0.2 mm. Min plated slot 0.65 mm, non-plated slot 0.8 mm. BGA pitch guidance: 0.45 mm pitch with 6/6 mil, 0.35 mm with 5/5 mil, 0.25 mm with 4/4 mil.++Sources:+- https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)+- https://www.seeedstudio.com/fusion_pcb.html (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/seeed-fusion-4L.druadded+71@@ -0,0 +1,71 @@+description[Seeed Fusion 4-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option | Min spacing: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option | Min drill: 0.2 mm (7.87 mil) | Min via: 0.2 mm hole / 0.4 mm pad | Annular ring: via 0.1 mm | Copper to board edge: 0.3 mm | Hole to hole: 0.3 mm | Board thickness options: 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm | Copper weight options: 1 oz, 2 oz, 3 oz | Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold | Max board size: 500 x 500 mm | | Minimum trace width in inner layers for 4 layer boards: 0.15 mm (6 mil). Inner layer base copper 0.017 mm (0.5 oz), outer 0.035 to 0.07 mm (1 to 2 oz). Same trace width/spacing options by copper weight as 2 layer: 1 oz 4/4, 5/5, 6/6 mil; 2 oz 10/10 mil; 3 oz 15/15 mil. Min board size 10 x 10 mm. Castellated holes (plated half-holes) min 0.50 mm. | | Sources: | - https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 11.81mil+mdDrill = 11.81mil+msWidth = 4.0mil+msDrill = 7.87mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/seeed-fusion-4L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="seeed-fusion-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.2mm" preferredvalue="0.4mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.2mm" preferredvalue="0.4mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.3mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.3mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.2mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Seeed Fusion 4-layer design rules (standard process)++Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option+Min spacing: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option+Min drill: 0.2 mm (7.87 mil)+Min via: 0.2 mm hole / 0.4 mm pad+Annular ring: via 0.1 mm+Copper to board edge: 0.3 mm+Hole to hole: 0.3 mm+Board thickness options: 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm+Copper weight options: 1 oz, 2 oz, 3 oz+Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold+Max board size: 500 x 500 mm++Minimum trace width in inner layers for 4 layer boards: 0.15 mm (6 mil). Inner layer base copper 0.017 mm (0.5 oz), outer 0.035 to 0.07 mm (1 to 2 oz). Same trace width/spacing options by copper weight as 2 layer: 1 oz 4/4, 5/5, 6/6 mil; 2 oz 10/10 mil; 3 oz 15/15 mil. Min board size 10 x 10 mm. Castellated holes (plated half-holes) min 0.50 mm.++Sources:+- https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/seeed-fusion-6L.druadded+71@@ -0,0 +1,71 @@+description[Seeed Fusion 6-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option | Min spacing: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option | Min drill: 0.2 mm (7.87 mil) | Min via: 0.2 mm hole / 0.4 mm pad | Annular ring: via 0.1 mm | Copper to board edge: 0.3 mm | Hole to hole: 0.3 mm | Board thickness options: 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm | Copper weight options: 1 oz, 2 oz, 3 oz | Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold | Max board size: 500 x 500 mm | | Seeed standard service supports 1 to 6 layers (layers table extends to 16). Board thickness options listed are for 6 and 8 layer boards. Inner layer trace width limit not separately published for 6 layer; 4 layer value is 0.15 mm (6 mil). | | Sources: | - https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)]++layerSetup = (1*2*3*14*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 11.81mil+mdDrill = 11.81mil+msWidth = 4.0mil+msDrill = 7.87mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 3.94mil+rlMaxViaOuter = 20mil+rlMinViaInner = 3.94mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 3.94mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 3.94mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/seeed-fusion-6L.edruadded+144@@ -0,0 +1,144 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="seeed-fusion-6L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.2mm" preferredvalue="0.4mm" name="Min Via hole size on 6-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.2mm" preferredvalue="0.4mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.3mm" preferredvalue="0.3mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.3mm"/>+<param name="mdDrill" value="0.3mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.2mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Seeed Fusion 6-layer design rules (standard process)++Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option+Min spacing: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option+Min drill: 0.2 mm (7.87 mil)+Min via: 0.2 mm hole / 0.4 mm pad+Annular ring: via 0.1 mm+Copper to board edge: 0.3 mm+Hole to hole: 0.3 mm+Board thickness options: 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm+Copper weight options: 1 oz, 2 oz, 3 oz+Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold+Max board size: 500 x 500 mm++Seeed standard service supports 1 to 6 layers (layers table extends to 16). Board thickness options listed are for 6 and 8 layer boards. Inner layer trace width limit not separately published for 6 layer; 4 layer value is 0.15 mm (6 mil).++Sources:+- https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*3*14*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/seeed-fusion-advanced-2L.druadded+71@@ -0,0 +1,71 @@+description[Seeed Fusion 2-layer design rules (advanced process) | | Min trace width: 0.127 mm (5.0 mil) - outer layer, 1 oz copper | Min spacing: 0.127 mm (5.0 mil) - outer layer, 1 oz copper | Min drill: 0.1 mm (3.94 mil) | Min via: 0.1 mm hole / 0.3032 mm pad | Annular ring: via 0.1016 mm | Hole to hole: 0.2286 mm | Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz | Surface finishes: HASL, HASL lead-free, ENIG, Hard Gold, Immersion Tin, Immersion Silver, OSP | Max board size: n/a x n/a mm | | Outer layer trace/spacing by copper weight: 1/3 oz 3/3 mil (0.0762 mm), 0.5 oz 4/4 mil (0.1016 mm), 1 oz 5/5 mil (0.127 mm), 2 oz 6/8 mil (0.1524/0.2032 mm), 3 oz 7/10 mil (0.1778/0.254 mm), 4 oz 8/13 mil (0.2032/0.3302 mm), 5 oz 10/16 mil (0.254/0.4064 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). Board thickness rigid 0.2 to 8.0 mm. Min castellated hole diameter 0.35 mm. Plugged vias finished diameter 0.15 to 0.8 mm. HDI stacks 1+n+1, 1+1+n+1+1, 2+n+2. Outline, V-cut and milling slot tolerance 0.10 mm. Solder mask colors include purple, matte green, customized. Board size limits not published on this page. | | Sources: | - https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 5.0mil+mdWirePad = 5.0mil+mdWireVia = 5.0mil+mdPadPad = 5.91mil+mdPadVia = 5.0mil+mdViaVia = 5.0mil+mdSmdPad = 5.0mil+mdSmdVia = 5.0mil+mdSmdSmd = 5.0mil+mdCopperDimension = 7.87mil+mdDrill = 9.0mil+msWidth = 5.0mil+msDrill = 3.94mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/seeed-fusion-advanced-2L.edruadded+142@@ -0,0 +1,142 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="seeed-fusion-advanced-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.127mm" preferredvalue="0.381mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.127mm" preferredvalue="0.254mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1mm" preferredvalue="0.2mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1mm" preferredvalue="0.25mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.127mm" preferredvalue="0.254mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2286mm" preferredvalue="0.2286mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.127mm"/>+<param name="mdWirePad" value="0.127mm"/>+<param name="mdWireVia" value="0.127mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.127mm"/>+<param name="mdViaVia" value="0.127mm"/>+<param name="mdSmdPad" value="0.127mm"/>+<param name="mdSmdVia" value="0.127mm"/>+<param name="mdSmdSmd" value="0.127mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2286mm"/>+<param name="msWidth" value="0.127mm"/>+<param name="msDrill" value="0.1mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Seeed Fusion 2-layer design rules (advanced process)++Min trace width: 0.127 mm (5.0 mil) - outer layer, 1 oz copper+Min spacing: 0.127 mm (5.0 mil) - outer layer, 1 oz copper+Min drill: 0.1 mm (3.94 mil)+Min via: 0.1 mm hole / 0.3032 mm pad+Annular ring: via 0.1016 mm+Hole to hole: 0.2286 mm+Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+Surface finishes: HASL, HASL lead-free, ENIG, Hard Gold, Immersion Tin, Immersion Silver, OSP+Max board size: n/a x n/a mm++Outer layer trace/spacing by copper weight: 1/3 oz 3/3 mil (0.0762 mm), 0.5 oz 4/4 mil (0.1016 mm), 1 oz 5/5 mil (0.127 mm), 2 oz 6/8 mil (0.1524/0.2032 mm), 3 oz 7/10 mil (0.1778/0.254 mm), 4 oz 8/13 mil (0.2032/0.3302 mm), 5 oz 10/16 mil (0.254/0.4064 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). Board thickness rigid 0.2 to 8.0 mm. Min castellated hole diameter 0.35 mm. Plugged vias finished diameter 0.15 to 0.8 mm. HDI stacks 1+n+1, 1+1+n+1+1, 2+n+2. Outline, V-cut and milling slot tolerance 0.10 mm. Solder mask colors include purple, matte green, customized. Board size limits not published on this page.++Sources:+- https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1016mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1016mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1016mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1016mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/seeed-fusion-advanced-4L.druadded+71@@ -0,0 +1,71 @@+description[Seeed Fusion 4-layer design rules (advanced process) | | Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1 oz copper | Min spacing: 0.1016 mm (4.0 mil) - inner layer, 1 oz copper | Min drill: 0.1 mm (3.94 mil) | Min via: 0.1 mm hole / 0.3032 mm pad | Annular ring: via 0.1016 mm | Hole to hole: 0.2286 mm | Copper weight options: 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz | Surface finishes: HASL, HASL lead-free, ENIG, Hard Gold, Immersion Tin, Immersion Silver, OSP | Max board size: n/a x n/a mm | | Inner layer trace/spacing by copper weight: 0.5 oz 3/3 mil (0.0762 mm), 1 oz 4/4 mil (0.1016 mm), 2 oz 5/6 mil (0.127/0.1524 mm), 3 oz 7/9 mil (0.1778/0.2286 mm), 4 oz 8/12 mil (0.2032/0.3048 mm), 5 oz 10/15 mil (0.254/0.381 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). For outer layer values see the 2 layer entry. FR4 1 to 30 layers, rigid-flex up to 36 rigid layers, board thickness rigid 0.2 to 8.0 mm. Back drilling diameter 0.5 to 6.3 mm, depth tolerance 0.10 mm. Min BGA pad diameter 7 mil (0.1778 mm) with 4/4 mil trace/spacing. | | Sources: | - https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 7.87mil+mdDrill = 9.0mil+msWidth = 4.0mil+msDrill = 3.94mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 4.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 4.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 4.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 4.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/seeed-fusion-advanced-4L.edruadded+142@@ -0,0 +1,142 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="seeed-fusion-advanced-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.1mm" preferredvalue="0.2mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.1mm" preferredvalue="0.25mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2286mm" preferredvalue="0.2286mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.2mm"/>+<param name="mdDrill" value="0.2286mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.1mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Seeed Fusion 4-layer design rules (advanced process)++Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1 oz copper+Min spacing: 0.1016 mm (4.0 mil) - inner layer, 1 oz copper+Min drill: 0.1 mm (3.94 mil)+Min via: 0.1 mm hole / 0.3032 mm pad+Annular ring: via 0.1016 mm+Hole to hole: 0.2286 mm+Copper weight options: 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+Surface finishes: HASL, HASL lead-free, ENIG, Hard Gold, Immersion Tin, Immersion Silver, OSP+Max board size: n/a x n/a mm++Inner layer trace/spacing by copper weight: 0.5 oz 3/3 mil (0.0762 mm), 1 oz 4/4 mil (0.1016 mm), 2 oz 5/6 mil (0.127/0.1524 mm), 3 oz 7/9 mil (0.1778/0.2286 mm), 4 oz 8/12 mil (0.2032/0.3048 mm), 5 oz 10/15 mil (0.254/0.381 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). For outer layer values see the 2 layer entry. FR4 1 to 30 layers, rigid-flex up to 36 rigid layers, board thickness rigid 0.2 to 8.0 mm. Back drilling diameter 0.5 to 6.3 mm, depth tolerance 0.10 mm. Min BGA pad diameter 7 mil (0.1778 mm) with 4/4 mil trace/spacing.++Sources:+- https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.1016mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.1016mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.1016mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.1016mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/sierra-circuits-2L.druadded+71@@ -0,0 +1,71 @@+description[Sierra Circuits 2-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - STANDARD tier | Min spacing: 0.1016 mm (4.0 mil) - STANDARD tier | Min drill: 0.15 mm (5.9 mil) | Min via: 0.15 mm hole / 0.4547 mm pad | Annular ring: via 0.0254 mm | Copper to board edge: 0.254 mm | Board thickness options: 0.254 mm, 7.62 mm | Copper weight options: 4 oz | Surface finishes: HASL, Lead-Free HASL, OSP (Shikoku F2), OSP (Entek), ENIG, Immersion Silver, Electrolytic Soft Gold, Electrolytic Hard Gold, Selective Gold | Max board size: 304.8 x 457.2 mm | | Values from the rigid PCB STANDARD tier table, published per process tier, not broken out by layer count, so 2-layer uses the same STANDARD values. Min board thickness 0.010 in (0.254 mm), max 0.300 in (7.62 mm). Max finished copper: outer layer 4 oz, inner layer 4 oz, min starting foil 3 microns. Min via pad derived from published process pad formula D plus 0.012 in, i.e. min drill 5.9 mil plus 12 mil. Annular ring 1 mil as stated in the process pad row. Max panel size STANDARD tier 12 x 18 in. Smallest laser drill 5 mil (0.127 mm), min finished hole 4 mil (0.102 mm). Solder mask registration 2 mil (0.0508 mm), solder mask feature tolerance 1.5 mil (0.0381 mm). | | Sources: | - https://www.protoexpress.com/products/rigid-pcb/ (read 2026-09-03)]++layerSetup = (1*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 10.0mil+mdDrill = 7.87mil+msWidth = 4.0mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 1.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 1.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 1.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 1.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/sierra-circuits-2L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="sierra-circuits-2L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 2-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.254mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.254mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Sierra Circuits 2-layer design rules (standard process)++Min trace width: 0.1016 mm (4.0 mil) - STANDARD tier+Min spacing: 0.1016 mm (4.0 mil) - STANDARD tier+Min drill: 0.15 mm (5.9 mil)+Min via: 0.15 mm hole / 0.4547 mm pad+Annular ring: via 0.0254 mm+Copper to board edge: 0.254 mm+Board thickness options: 0.254 mm, 7.62 mm+Copper weight options: 4 oz+Surface finishes: HASL, Lead-Free HASL, OSP (Shikoku F2), OSP (Entek), ENIG, Immersion Silver, Electrolytic Soft Gold, Electrolytic Hard Gold, Selective Gold+Max board size: 304.8 x 457.2 mm++Values from the rigid PCB STANDARD tier table, published per process tier, not broken out by layer count, so 2-layer uses the same STANDARD values. Min board thickness 0.010 in (0.254 mm), max 0.300 in (7.62 mm). Max finished copper: outer layer 4 oz, inner layer 4 oz, min starting foil 3 microns. Min via pad derived from published process pad formula D plus 0.012 in, i.e. min drill 5.9 mil plus 12 mil. Annular ring 1 mil as stated in the process pad row. Max panel size STANDARD tier 12 x 18 in. Smallest laser drill 5 mil (0.127 mm), min finished hole 4 mil (0.102 mm). Solder mask registration 2 mil (0.0508 mm), solder mask feature tolerance 1.5 mil (0.0381 mm).++Sources:+- https://www.protoexpress.com/products/rigid-pcb/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0254mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0254mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0254mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0254mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
fusion/sierra-circuits-4L.druadded+71@@ -0,0 +1,71 @@+description[Sierra Circuits 4-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - STANDARD tier | Min spacing: 0.1016 mm (4.0 mil) - STANDARD tier | Min drill: 0.15 mm (5.9 mil) | Min via: 0.15 mm hole / 0.4547 mm pad | Annular ring: via 0.0254 mm | Copper to board edge: 0.254 mm | Board thickness options: 0.254 mm, 7.62 mm | Copper weight options: 4 oz | Surface finishes: HASL, Lead-Free HASL, OSP (Shikoku F2), OSP (Entek), ENIG, Immersion Silver, Electrolytic Soft Gold, Electrolytic Hard Gold, Selective Gold | Max board size: 304.8 x 457.2 mm | | Same STANDARD tier table as 2-layer, Sierra does not publish separate 4-layer limits on this page. Blind and buried vias available. Controlled impedance tolerance 10 percent STANDARD tier. | | Sources: | - https://www.protoexpress.com/products/rigid-pcb/ (read 2026-09-03)]++layerSetup = (1*2*15*16)+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm+mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm+mdWireWire = 4.0mil+mdWirePad = 4.0mil+mdWireVia = 4.0mil+mdPadPad = 5.91mil+mdPadVia = 4.0mil+mdViaVia = 4.0mil+mdSmdPad = 4.0mil+mdSmdVia = 4.0mil+mdSmdSmd = 4.0mil+mdCopperDimension = 10.0mil+mdDrill = 7.87mil+msWidth = 4.0mil+msDrill = 5.91mil+mdViaViaSameLayer = 6mil+mdSmdStop = 0mil+msMicroVia = 12mil+msBlindViaRatio = 0.5+rvPadTop = 0+rvPadInner = 0+rvPadBottom = 0+rvViaOuter = 0+rvViaInner = 0+rvMicroViaOuter = 0+rvMicroViaInner = 0+rlMinPadTop = 7.09mil+rlMaxPadTop = 80mil+rlMinPadInner = 7.09mil+rlMaxPadInner = 20mil+rlMinPadBottom = 7.09mil+rlMaxPadBottom = 80mil+rlMinViaOuter = 1.0mil+rlMaxViaOuter = 20mil+rlMinViaInner = 1.0mil+rlMaxViaInner = 20mil+rlMinMicroViaOuter = 1.0mil+rlMaxMicroViaOuter = 20mil+rlMinMicroViaInner = 1.0mil+rlMaxMicroViaInner = 20mil+psTop = -1+psBottom = -1+psFirst = -1+psElongationLong = 100+psElongationOffset = 100+mvStopFrame = 0+mvCreamFrame = 0+mlMinStopFrame = 1.5mil+mlMaxStopFrame = 4mil+mlMinCreamFrame = 0mil+mlMaxCreamFrame = 0mil+mlViaStopLimit = 20mil+srRoundness = 0+srMinRoundness = 0mil+srMaxRoundness = 0mil+slThermalIsolate = 10mil+slThermalsForVias = 0+dpMaxLengthDifference = 400mil+dpGapFactor = 2.5+checkAngle = 0+checkRestrict = 1+checkStop = 0+checkValues = 0+checkNames = 1+checkWireStubs = 1+checkPolygonWidth = 0+useDiameter = 13+maxErrors = 50
fusion/sierra-circuits-4L.edruadded+143@@ -0,0 +1,143 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE designrules SYSTEM "eagle.dtd">+<eagle version="9.7.0">+<designrules name="sierra-circuits-4L.edru">+<classes>+<class number="0" name="default">+</class>+<class number="1" name="pwr">+</class>+</classes>+<rules>+<rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Solder-Mask Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Dimension Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Drill Distance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Drill Size" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Minimum Copper Width" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Acute Angle" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Air-Wire" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Small Gap" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Wire Stub" manualdrc="yes" livedrc="no"/>+ <rulecategory type="Matched Lengths" manualdrc="yes" livedrc="yes"/>+ <rulecategory type="Via Restrict Clearance" manualdrc="yes" livedrc="yes"/>+ <rule type="Minimum Copper Width" enabled="yes" priority="0" onescope="classes=1" value="0.1016mm" preferredvalue="0.3048mm" check_polywidth="no" name="Trace size for Power"/>+ <rule type="Minimum Copper Width" builtin_ruleid="14" enabled="yes" priority="1" value="0.1016mm" preferredvalue="0.2032mm" check_polywidth="no" name="minimum-copper-width-1"/>+ <rule type="Minimum Drill Size" enabled="yes" priority="0" onescope="is_via" value="0.15mm" preferredvalue="0.3mm" name="Min Via hole size on 4-layer"/>+ <rule type="Minimum Drill Size" enabled="no" priority="1" onescope="all" value="0.5mm" preferredvalue="0.5mm" name="Min Non-plated holes"/>+ <rule type="Minimum Drill Size" builtin_ruleid="15" enabled="yes" priority="2" value="0.15mm" preferredvalue="0.3mm" name="minimum-drill-size-1"/>+ <rule type="Acute Angle" builtin_ruleid="16" enabled="no" priority="0" name="acute-angle-1"/>+ <rule type="Wire Stub" builtin_ruleid="17" enabled="yes" priority="0" name="wire-stub-1"/>+ <rule type="Air-Wire" builtin_ruleid="19" enabled="yes" priority="0" name="air-wire-1"/>+ <rule type="Matched Lengths" builtin_ruleid="20" enabled="yes" priority="0" tolerance="10mm" gapfactor="2.5" name="matched-lengths-1"/>+ <rule type="Copper Clearance" enabled="yes" priority="0" onescope="all" otherscope="all" value="0.25mm" preferredvalue="0.25mm" samesignal="yes" bothscope="all" name="Same-net track spacing"/>+ <rule type="Copper Clearance" builtin_ruleid="0" enabled="yes" priority="1" onescope="is_wire_polygon" otherscope="is_wire_polygon" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-1"/>+ <rule type="Copper Clearance" builtin_ruleid="1" enabled="yes" priority="2" onescope="is_wire_polygon" otherscope="is_pad_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-2"/>+ <rule type="Copper Clearance" builtin_ruleid="2" enabled="yes" priority="3" onescope="is_wire_polygon" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-3"/>+ <rule type="Copper Clearance" builtin_ruleid="3" enabled="yes" priority="4" onescope="is_pad_smd" otherscope="is_pad_smd" value="0.15mm" preferredvalue="0.15mm" samesignal="no" name="copper-clearance-4"/>+ <rule type="Copper Clearance" builtin_ruleid="4" enabled="yes" priority="5" onescope="is_pad_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-5"/>+ <rule type="Copper Clearance" builtin_ruleid="5" enabled="yes" priority="6" onescope="is_via" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="no" name="copper-clearance-6"/>+ <rule type="Copper Clearance" builtin_ruleid="6" enabled="yes" priority="7" onescope="is_smd" otherscope="is_pad" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-7"/>+ <rule type="Copper Clearance" builtin_ruleid="7" enabled="yes" priority="8" onescope="is_smd" otherscope="is_via" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-8"/>+ <rule type="Copper Clearance" builtin_ruleid="8" enabled="yes" priority="9" onescope="is_smd" otherscope="is_smd" value="0.1016mm" preferredvalue="0.2032mm" samesignal="yes" name="copper-clearance-9"/>+ <rule type="Dimension Clearance" builtin_ruleid="9" enabled="yes" priority="0" value="0.254mm" preferredvalue="0.4mm" name="dimension-clearance-1"/>+ <rule type="Via Restrict Clearance" builtin_ruleid="21" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="via-restrict-clearance-1"/>+ <rule type="Restrict Clearance" builtin_ruleid="10" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="restrict-clearance-1"/>+ <rule type="Small Gap" builtin_ruleid="18" enabled="yes" priority="0" name="small-gap-1"/>+ <rule type="Solder-Mask Clearance" builtin_ruleid="11" enabled="no" priority="0" value="0mil" preferredvalue="0mil" check_name="yes" check_value="no" name="solder-mask-clearance-1"/>+ <rule type="Drill Distance" builtin_ruleid="12" enabled="yes" priority="0" value="0.2mm" preferredvalue="0.2mm" name="drill-distance-1"/>+ <rule type="Keepout Clearance" builtin_ruleid="13" enabled="yes" priority="0" value="0mil" preferredvalue="0mil" name="keepout-clearance-1"/>+ </rules>+<param name="mdWireWire" value="0.1016mm"/>+<param name="mdWirePad" value="0.1016mm"/>+<param name="mdWireVia" value="0.1016mm"/>+<param name="mdPadPad" value="0.15mm"/>+<param name="mdPadVia" value="0.1016mm"/>+<param name="mdViaVia" value="0.1016mm"/>+<param name="mdSmdPad" value="0.1016mm"/>+<param name="mdSmdVia" value="0.1016mm"/>+<param name="mdSmdSmd" value="0.1016mm"/>+<param name="mdCopperDimension" value="0.254mm"/>+<param name="mdDrill" value="0.2mm"/>+<param name="msWidth" value="0.1016mm"/>+<param name="msDrill" value="0.15mm"/>+<param name="dpMaxLengthDifference" value="10mm"/>+<param name="dpGapFactor" value="2.5"/>+<description language="en">Sierra Circuits 4-layer design rules (standard process)++Min trace width: 0.1016 mm (4.0 mil) - STANDARD tier+Min spacing: 0.1016 mm (4.0 mil) - STANDARD tier+Min drill: 0.15 mm (5.9 mil)+Min via: 0.15 mm hole / 0.4547 mm pad+Annular ring: via 0.0254 mm+Copper to board edge: 0.254 mm+Board thickness options: 0.254 mm, 7.62 mm+Copper weight options: 4 oz+Surface finishes: HASL, Lead-Free HASL, OSP (Shikoku F2), OSP (Entek), ENIG, Immersion Silver, Electrolytic Soft Gold, Electrolytic Hard Gold, Selective Gold+Max board size: 304.8 x 457.2 mm++Same STANDARD tier table as 2-layer, Sierra does not publish separate 4-layer limits on this page. Blind and buried vias available. Controlled impedance tolerance 10 percent STANDARD tier.++Sources:+- https://www.protoexpress.com/products/rigid-pcb/ (read 2026-09-03)+</description>+<param name="layerSetup" value="(1*2*15*16)"/>+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>+<param name="mtIsolate" value="1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>+<param name="mdViaViaSameLayer" value="6mil"/>+<param name="mnLayersViaInSmd" value="2"/>+<param name="mdSmdStop" value="0mil"/>+<param name="msMicroVia" value="0.3mm"/>+<param name="msBlindViaRatio" value="0.5"/>+<param name="rvPadTop" value="0"/>+<param name="rvPadInner" value="0"/>+<param name="rvPadBottom" value="0"/>+<param name="rvViaOuter" value="0"/>+<param name="rvViaInner" value="0"/>+<param name="rvMicroViaOuter" value="0"/>+<param name="rvMicroViaInner" value="0"/>+<param name="rlMinPadTop" value="0.18mm"/>+<param name="rlMaxPadTop" value="80mil"/>+<param name="rlMinPadInner" value="0.18mm"/>+<param name="rlMaxPadInner" value="20mil"/>+<param name="rlMinPadBottom" value="0.18mm"/>+<param name="rlMaxPadBottom" value="80mil"/>+<param name="rlMinViaOuter" value="0.0254mm"/>+<param name="rlMaxViaOuter" value="20mil"/>+<param name="rlMinViaInner" value="0.0254mm"/>+<param name="rlMaxViaInner" value="20mil"/>+<param name="rlMinMicroViaOuter" value="0.0254mm"/>+<param name="rlMaxMicroViaOuter" value="20mil"/>+<param name="rlMinMicroViaInner" value="0.0254mm"/>+<param name="rlMaxMicroViaInner" value="20mil"/>+<param name="psTop" value="-1"/>+<param name="psBottom" value="-1"/>+<param name="psFirst" value="-1"/>+<param name="psElongationLong" value="100"/>+<param name="psElongationOffset" value="100"/>+<param name="mvStopFrame" value="0"/>+<param name="mvCreamFrame" value="0"/>+<param name="mlMinStopFrame" value="0.038mm"/>+<param name="mlMaxStopFrame" value="4mil"/>+<param name="mlMinCreamFrame" value="0mil"/>+<param name="mlMaxCreamFrame" value="0mil"/>+<param name="mlViaStopLimit" value="0.5mm"/>+<param name="srRoundness" value="0"/>+<param name="srMinRoundness" value="0mil"/>+<param name="srMaxRoundness" value="0mil"/>+<param name="slThermalIsolate" value="10mil"/>+<param name="slThermalsForVias" value="0"/>+<param name="checkAngle" value="0"/>+<param name="checkRestrict" value="1"/>+<param name="checkStop" value="0"/>+<param name="checkValues" value="0"/>+<param name="checkNames" value="1"/>+<param name="checkWireStubs" value="1"/>+<param name="checkPolygonWidth" value="0"/>+<param name="useDiameter" value="13"/>+<param name="removeAnnularRing" value="0"/>+<param name="maxErrors" value="50"/>+ </designrules>+</eagle>
kicad/adom-instapcb-2L.board-setup.jsonadded+26@@ -0,0 +1,26 @@+{+ "vendor": "Adom InstaPCB",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1,+ "minClearanceMm": 0.1,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.25,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.2,+ "annularRingViaMm": 0.1,+ "annularRingPadMm": 0.18,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": 0.038+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru",+ "dateRead": "2026-09-03",+ "kind": "bundled-house-rule-file"+ }+ ]+}
kicad/adom-instapcb-2L.kicad_druadded+40@@ -0,0 +1,40 @@+(version 1)++# Adom InstaPCB 2-layer design rules (standard process)+# +# Min trace width: 0.1 mm (3.94 mil) - 1 oz copper+# Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.1 mm, pad 0.18 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.2 mm+# Drill range: 0.15 mm to 6.3 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# +# House baseline of the Adom InstaPCB fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.+# +# Sources:+# - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.25mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))
kicad/adom-instapcb-4L.board-setup.jsonadded+26@@ -0,0 +1,26 @@+{+ "vendor": "Adom InstaPCB",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.09,+ "minClearanceMm": 0.09,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.25,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.2,+ "annularRingViaMm": 0.1,+ "annularRingPadMm": 0.18,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": 0.038+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru",+ "dateRead": "2026-09-03",+ "kind": "bundled-house-rule-file"+ }+ ]+}
kicad/adom-instapcb-4L.kicad_druadded+40@@ -0,0 +1,40 @@+(version 1)++# Adom InstaPCB 4-layer design rules (standard process)+# +# Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer+# Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.1 mm, pad 0.18 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.2 mm+# Drill range: 0.15 mm to 6.3 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# +# BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias.+# +# Sources:+# - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.09mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.09mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.25mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))
kicad/advanced-circuits-4pcb-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Advanced Circuits (4PCB)",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.127,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.254,+ "minViaDiameterMm": null,+ "minHoleMm": 0.254,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": null,+ "annularRingViaMm": null,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.4pcb.com/laminate-material-vendors.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/advanced-circuits-4pcb-2L.kicad_druadded+30@@ -0,0 +1,30 @@+(version 1)++# Advanced Circuits (4PCB) 2-layer design rules (standard process)+# +# Min trace width: 0.127 mm (5.0 mil) - outer trace, standard spec+# Min spacing: 0.127 mm (5.0 mil) - standard spec trace/space 5/5 mils+# Min drill: 0.254 mm (10.0 mil)+# Min via: 0.254 mm hole+# Board thickness options: 0.7874 mm, 1.5748 mm, 2.3622 mm, 3.175 mm+# Copper weight options: 1 oz, 2 oz+# Surface finishes: Lead-Free HAL+# Max board size: 406.4 x 558.8 mm+# +# Standard spec: FR-4, 0 to 12 layers, IPC Class 2, quantity 1 to 10000 plus, turn time same day to 5 day. Hole tolerance plus or minus 0.005 in (0.127 mm). Rout tolerance plus or minus 0.010 in (0.254 mm). Solder mask LPI green, legend white. Board thickness options 0.031, 0.062, 0.093, 0.125 in. Standard finish pricing assumes lead-free HAL; ENIG or immersion silver at no extra cost if HAL unavailable. Same spec applies to 2 and 4 layer; page does not differentiate by layer count below 12.+# +# Sources:+# - https://www.4pcb.com/laminate-material-vendors.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.127mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.254mm))+ (condition "A.type == 'pad' || A.type == 'via'"))
kicad/advanced-circuits-4pcb-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Advanced Circuits (4PCB)",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.127,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.254,+ "minViaDiameterMm": null,+ "minHoleMm": 0.254,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": null,+ "annularRingViaMm": null,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.4pcb.com/laminate-material-vendors.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/advanced-circuits-4pcb-4L.kicad_druadded+30@@ -0,0 +1,30 @@+(version 1)++# Advanced Circuits (4PCB) 4-layer design rules (standard process)+# +# Min trace width: 0.127 mm (5.0 mil) - outer trace, standard spec+# Min spacing: 0.127 mm (5.0 mil) - standard spec trace/space 5/5 mils+# Min drill: 0.254 mm (10.0 mil)+# Min via: 0.254 mm hole+# Board thickness options: 0.7874 mm, 1.5748 mm, 2.3622 mm, 3.175 mm+# Copper weight options: 1 oz, 2 oz+# Surface finishes: Lead-Free HAL+# Max board size: 406.4 x 558.8 mm+# +# Same standard spec as 2 layer. Typical 4-layer stackup published at 0.020, 0.031, 0.062, 0.093, 0.125 in finished thickness with 1 oz copper, max board size 16 x 22 in for 0.031 to 0.093 in, 14 x 20 in (355.6 x 508 mm) at 0.125 in.+# +# Sources:+# - https://www.4pcb.com/laminate-material-vendors.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.127mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.254mm))+ (condition "A.type == 'pad' || A.type == 'via'"))
kicad/advanced-circuits-4pcb-advanced-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Advanced Circuits (4PCB)",+ "process": "advanced",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.127,+ "minViaDiameterMm": 0.508,+ "minHoleMm": 0.127,+ "copperEdgeClearanceMm": 0.2032,+ "holeToHoleMm": 0.254,+ "annularRingViaMm": 0.1905,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.0762,+ "maskExpansionMm": 0.0508+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/advanced-circuits-4pcb-advanced-2L.kicad_druadded+44@@ -0,0 +1,44 @@+(version 1)++# Advanced Circuits (4PCB) 2-layer design rules (advanced process)+# +# Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz base, 0.0762 mm (3 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz; inner 1 oz: 0.0889 mm (3.5 mil)+# Min spacing: 0.1016 mm (4.0 mil) - outer layer trace to trace, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz, 0.0635 mm (2.5 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz+# Min drill: 0.127 mm (5.0 mil)+# Min via: 0.127 mm hole / 0.508 mm pad+# Annular ring: via 0.1905 mm+# Copper to board edge: 0.2032 mm+# Hole to hole: 0.254 mm+# Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+# Max board size: 482.6 x 558.8 mm+# +# Santa Clara CA, Advanced tier. Max board size 19 x 22 in. Min board thickness 0.008 in (0.2032 mm). PTH tolerance plus or minus 0.002 in (0.0508 mm). Minimum pad 0.01 in (0.254 mm). Min outer layer trace for filled and plated over vias 0.004 in (0.1016 mm). Aspect ratio PTH 12:1.+# +# Sources:+# - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.127mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.508mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2032mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.0762mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/advanced-circuits-4pcb-advanced-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Advanced Circuits (4PCB)",+ "process": "advanced",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.127,+ "minViaDiameterMm": 0.508,+ "minHoleMm": 0.127,+ "copperEdgeClearanceMm": 0.2032,+ "holeToHoleMm": 0.254,+ "annularRingViaMm": 0.1905,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.0762,+ "maskExpansionMm": 0.0508+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/advanced-circuits-4pcb-advanced-4L.kicad_druadded+44@@ -0,0 +1,44 @@+(version 1)++# Advanced Circuits (4PCB) 4-layer design rules (advanced process)+# +# Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz Cu base; inner 1 oz: 0.0889 mm (3.5 mil)+# Min spacing: 0.1016 mm (4.0 mil) - outer layer trace to trace, 1 oz Cu base; inner 1 oz: 0.1016 mm (4 mil)+# Min drill: 0.127 mm (5.0 mil)+# Min via: 0.127 mm hole / 0.508 mm pad+# Annular ring: via 0.1905 mm+# Copper to board edge: 0.2032 mm+# Hole to hole: 0.254 mm+# Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+# Max board size: 482.6 x 558.8 mm+# +# Same Advanced tier values as 2 layer for this facility.+# +# Sources:+# - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.127mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.508mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2032mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.0762mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/advanced-circuits-4pcb-advanced-standard-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Advanced Circuits (4PCB)",+ "process": "advanced-standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1397,+ "minClearanceMm": 0.1397,+ "minViaDrillMm": 0.1499,+ "minViaDiameterMm": 0.5309,+ "minHoleMm": 0.1499,+ "copperEdgeClearanceMm": 0.254,+ "holeToHoleMm": 0.3048,+ "annularRingViaMm": 0.1905,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1016,+ "maskExpansionMm": 0.0762+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/advanced-circuits-4pcb-advanced-standard-2L.kicad_druadded+44@@ -0,0 +1,44 @@+(version 1)++# Advanced Circuits (4PCB) 2-layer design rules (advanced-standard process)+# +# Min trace width: 0.1397 mm (5.5 mil) - outer layer, 1 oz Cu base; other weights: 0.0762 mm (3 mil) at 1/4 and 3/8 oz base, 0.1143 mm (4.5 mil) at 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)+# Min spacing: 0.1397 mm (5.5 mil) - outer layer trace to trace, 1 oz Cu base; 0.0762 mm (3 mil) at 1/4, 3/8, 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)+# Min drill: 0.1499 mm (5.9 mil)+# Min via: 0.1499 mm hole / 0.5309 mm pad+# Annular ring: via 0.1905 mm+# Copper to board edge: 0.254 mm+# Hole to hole: 0.3048 mm+# Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+# Max board size: 406.4 x 558.8 mm+# +# Capabilities table is per facility and per tier; this object is Santa Clara, CA, Standard column. Min board thickness 0.01 in (0.254 mm), max board thickness 0.25 in (6.35 mm). PTH tolerance plus or minus 0.003 in (0.0762 mm). Drill to copper for PTH 0.01 in (0.254 mm). Minimum pad 0.015 in (0.381 mm), minimum isolated pad 0.01 in (0.254 mm). Min copper sliver between antipads 0.005 in (0.127 mm). Aspect ratio plated through holes 10:1 for drilled greater than 0.020 in, 10:1 for 0.010 to 0.019 in. Other facilities differ, e.g. Maple Grove MN standard outer 1 oz trace width is 0.1016 mm (4 mil), smallest mech via 0.0043 in (0.1092 mm).+# +# Sources:+# - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1397mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1397mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1499mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.5309mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.254mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1016mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/advanced-circuits-4pcb-advanced-standard-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Advanced Circuits (4PCB)",+ "process": "advanced-standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1397,+ "minClearanceMm": 0.1397,+ "minViaDrillMm": 0.1499,+ "minViaDiameterMm": 0.5309,+ "minHoleMm": 0.1499,+ "copperEdgeClearanceMm": 0.254,+ "holeToHoleMm": 0.3048,+ "annularRingViaMm": 0.1905,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1016,+ "maskExpansionMm": 0.0762+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/advanced-circuits-4pcb-advanced-standard-4L.kicad_druadded+44@@ -0,0 +1,44 @@+(version 1)++# Advanced Circuits (4PCB) 4-layer design rules (advanced-standard process)+# +# Min trace width: 0.1397 mm (5.5 mil) - outer layer, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil); inner 1/2 oz: 0.0889 mm (3.5 mil)+# Min spacing: 0.1397 mm (5.5 mil) - outer layer trace to trace, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil)+# Min drill: 0.1499 mm (5.9 mil)+# Min via: 0.1499 mm hole / 0.5309 mm pad+# Annular ring: via 0.1905 mm+# Copper to board edge: 0.254 mm+# Hole to hole: 0.3048 mm+# Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+# Max board size: 406.4 x 558.8 mm+# +# Same capabilities table values as 2 layer; buried vias mechanical drill minimum 0.0059 in (0.1499 mm), blind vias mechanical 0.0059 in, laser drilled blind via minimum 0.004 in (0.1016 mm).+# +# Sources:+# - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1397mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1397mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1499mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.5309mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.254mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1016mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/aisler-enig-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Aisler",+ "process": "enig",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.125,+ "minClearanceMm": 0.125,+ "minViaDrillMm": 0.25,+ "minViaDiameterMm": 0.45,+ "minHoleMm": 0.25,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": 0.3,+ "annularRingViaMm": 0.1,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.05+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/aisler-enig-2L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# Aisler 2-layer design rules (enig process)+# +# Min trace width: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish+# Min spacing: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish+# Min drill: 0.25 mm (10.0 mil)+# Min via: 0.25 mm hole / 0.45 mm pad+# Annular ring: via 0.1 mm+# Copper to board edge: 0.3 mm+# Hole to hole: 0.3 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# Surface finishes: ENIG+# Max board size: 500 x 500 mm+# +# Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Min SMD pad size 200um (8 mil). Copper to NPTH clearance 250um (10 mil), copper to NPTH slot clearance 300um (12 mil) for slots under and over 1.8mm. PTH drill range 0.5mm to 5.6mm, PTH annular ring 300um. Via drill range 0.25mm to 0.45mm, via annular ring 100um. NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm, PTH slot annular ring 300um. Min silkscreen text height 800um (32 mil). Max silkscreen coverage 25% per board side. Castellated edges supported free of charge. Green soldermask (Peters Elpemer AS 2467), buried, blind, micro, and tented vias not supported. Via pad diameter not published.+# +# Sources:+# - https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732 (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.125mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.125mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.25mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.45mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/aisler-enig-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Aisler",+ "process": "enig",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.125,+ "minClearanceMm": 0.125,+ "minViaDrillMm": 0.25,+ "minViaDiameterMm": 0.45,+ "minHoleMm": 0.25,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": 0.3,+ "annularRingViaMm": 0.1,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.05+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/aisler-enig-4L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# Aisler 4-layer design rules (enig process)+# +# Min trace width: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish+# Min spacing: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish+# Min drill: 0.25 mm (10.0 mil)+# Min via: 0.25 mm hole / 0.45 mm pad+# Annular ring: via 0.1 mm+# Copper to board edge: 0.3 mm+# Hole to hole: 0.3 mm+# Board thickness options: 0.8 mm, 1.6 mm+# Copper weight options: 1 oz+# Surface finishes: ENIG+# Max board size: 500 x 500 mm+# +# Source page states rules are valid for both 0.8mm and 1.6mm PCB thickness. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. PTH drill range 0.5mm to 5.6mm, via drill range 0.25mm to 0.45mm, via annular ring 100um, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges supported free of charge. Green soldermask. Via pad diameter not published.+# +# Sources:+# - https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733 (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.125mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.125mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.25mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.45mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/aisler-hasl-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Aisler",+ "process": "hasl",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.2,+ "minClearanceMm": 0.15,+ "minViaDrillMm": 0.3,+ "minViaDiameterMm": 0.7,+ "minHoleMm": 0.3,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": 0.3,+ "annularRingViaMm": 0.2,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.05+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/aisler-hasl-2L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# Aisler 2-layer design rules (hasl process)+# +# Min trace width: 0.2 mm (8.0 mil) - Cu 35um (1oz), HASL finish+# Min spacing: 0.15 mm (6.0 mil) - Cu 35um (1oz), HASL finish+# Min drill: 0.3 mm (12.0 mil)+# Min via: 0.3 mm hole / 0.7 mm pad+# Annular ring: via 0.2 mm+# Copper to board edge: 0.3 mm+# Hole to hole: 0.3 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# Surface finishes: HASL+# Max board size: 500 x 500 mm+# +# Lead-free HASL. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Via drill range 0.3mm to 0.45mm, drill may be enlarged up to 0.45mm. PTH drill range 0.5mm to 5.6mm, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges not supported with HASL. Green soldermask (Peters Elpemer AS 2467). Via pad diameter not published.+# +# Sources:+# - https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735 (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.2mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.15mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.3mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.7mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/allpcb-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "ALLPCB",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1,+ "minClearanceMm": 0.1,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.506,+ "minHoleMm": 0.2,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": 0.2032,+ "annularRingViaMm": 0.153,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.allpcb.com/standard_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/allpcb-2L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# ALLPCB 2-layer design rules (standard process)+# +# Min trace width: 0.1 mm (3.94 mil) - all copper weights; vendor suggests 6mil (0.15mm) or more to save cost+# Min spacing: 0.1 mm (3.94 mil) - all copper weights; vendor suggests 6mil (0.15mm) or more to save cost+# Min drill: 0.2 mm (7.87 mil)+# Min via: 0.2 mm hole / 0.506 mm pad+# Annular ring: via 0.153 mm+# Copper to board edge: 0.3 mm+# Hole to hole: 0.2032 mm+# Board thickness options: 0.4 mm, 3.2 mm+# Copper weight options: 0.5 oz, 1 oz, 2 oz+# Surface finishes: HASL, Immersion Gold, Immersion Silver, Immersion Tin, OSP, Hard Gold plating, Soft Gold plating, NiPdAu+# Max board size: 506 x 580 mm+# +# Single published limit set covers 1 to 14 layers, so this entry also applies to 4 and 6 layer boards. Board thickness is a continuous 0.4 to 3.2mm range. Copper: outer 1oz to 2oz (35 to 70um), inner 0.5oz to 2oz (18 to 70um). Min dimension 80x80mm. Drill range 0.2 to 6.5mm, finished CNC hole 0.2 to 6.5mm, hole size tolerance ±0.075mm. Copper to V-cut line 0.4mm (15.748mil) for panelized boards. Via space same net 8mil (0.2032mm), different nets 17mil (0.4318mm), component vias different nets 24mil (0.6096mm). Annular ring 6mil or larger where surrounded by traces. Min slot width 0.6mm, finished slot 0.45mm for HASL and 0.5mm for other finishes. Board thickness to via diameter ratio 6:1, 7:1 to 8:1 adds a fabrication day. Min character height 0.8mm (31.4961mil), width to height ratio 1:5. Mask sliver recorded from solder mask bridge value 0.1mm (price may rise).+# +# Sources:+# - https://www.allpcb.com/standard_pcb_manufacturing_capability.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.2mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.506mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/allpcb-advanced-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "ALLPCB",+ "process": "advanced",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.076,+ "minClearanceMm": 0.076,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.5,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": null,+ "annularRingViaMm": 0.18,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/allpcb-advanced-2L.kicad_druadded+45@@ -0,0 +1,45 @@+(version 1)++# ALLPCB 2-layer design rules (advanced process)+# +# Min trace width: 0.076 mm (3.0 mil) - 1oz copper+# Min spacing: 0.076 mm (3.0 mil) - 1oz copper+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.2 mm hole / 0.5 mm pad+# Annular ring: via 0.18 mm+# Copper to board edge: 0.3 mm+# Board thickness options: 0.4 mm, 4.0 mm+# Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+# Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating+# Max board size: 630 x 520 mm+# +# Double-side board via/pad: 0.2mm inner diameter, 0.5mm outer diameter; outer diameter must be 0.1mm larger than inner, 0.15mm preferred; preferred min via hole 0.2mm. Trace/spacing by copper weight: 1oz 0.076mm, 2oz 0.14mm (5.5118mil), 3oz 0.2mm (7.874mil), 4oz 0.25mm (9.8425mil), 5oz 0.35mm (13.7795mil), 6oz 0.45mm (17.7165mil). Trace width tolerance ±20%. Annular ring: plated DIP holes 1oz recommended 0.2mm, limit 0.18mm; non-plated DIP holes recommended 0.4mm (15.748mil). Min plated slot 0.7mm (27.5591mil), min non-plated slot 0.8mm (31.4961mil). Board thickness to min plated hole ratio 10:1. Plated half hole diameter 0.4mm or more, spacing 0.35mm (13.7795mil). Min single PCB size 10x5mm. Copper to board edge 0.3mm at non-stamp-hole panel areas; V-cut line to copper 0.4mm. Mask sliver recorded from min solder bridge width: green 0.075mm, other colors 0.125mm (4.9213mil). Silk text height 0.75mm (29.5276mil). BGA pad diameter 0.2mm or more. Edge rail 4mm or more.+# +# Sources:+# - https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.076mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.076mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.5mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/allpcb-advanced-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "ALLPCB",+ "process": "advanced",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.076,+ "minClearanceMm": 0.076,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.25,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": null,+ "annularRingViaMm": 0.18,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/allpcb-advanced-4L.kicad_druadded+45@@ -0,0 +1,45 @@+(version 1)++# ALLPCB 4-layer design rules (advanced process)+# +# Min trace width: 0.076 mm (3.0 mil) - 1oz copper+# Min spacing: 0.076 mm (3.0 mil) - 1oz copper+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.18 mm+# Copper to board edge: 0.3 mm+# Board thickness options: 0.4 mm, 4.0 mm+# Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+# Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating+# Max board size: 630 x 520 mm+# +# Multi-layer board via/pad: 0.15mm inner diameter, 0.25mm outer diameter. Other limits as 2 layer entry.+# +# Sources:+# - https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.076mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.076mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.25mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/allpcb-advanced-6L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "ALLPCB",+ "process": "advanced",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.076,+ "minClearanceMm": 0.076,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.25,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": null,+ "annularRingViaMm": 0.18,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/allpcb-advanced-6L.kicad_druadded+45@@ -0,0 +1,45 @@+(version 1)++# ALLPCB 6-layer design rules (advanced process)+# +# Min trace width: 0.076 mm (3.0 mil) - 1oz copper+# Min spacing: 0.076 mm (3.0 mil) - 1oz copper+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.18 mm+# Copper to board edge: 0.3 mm+# Board thickness options: 0.6 mm, 4.0 mm+# Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+# Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating+# Max board size: 630 x 520 mm+# +# 6 layer board thickness range 0.6 to 4.0mm, differs from 2 and 4 layer range 0.4 to 4.0mm. Other limits as 4 layer entry.+# +# Sources:+# - https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.076mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.076mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.25mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/elecrow-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Elecrow",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1524,+ "minClearanceMm": 0.1524,+ "minViaDrillMm": 0.3,+ "minViaDiameterMm": null,+ "minHoleMm": 0.3,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": null,+ "annularRingViaMm": null,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/elecrow-2L.kicad_druadded+35@@ -0,0 +1,35 @@+(version 1)++# Elecrow 2-layer design rules (standard process)+# +# Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil+# Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)+# Min drill: 0.3 mm (11.81 mil)+# Min via: 0.3 mm hole+# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+# Copper weight options: 1 oz, 2 oz+# Surface finishes: HASL, HASL Lead Free, ENIG+# Max board size: 550 x 550 mm+# +# Specs apply to regular custom PCB online ordering service, 1 to 8 layers share these limits. Maximum size 55cm x 55cm, minimum board dimension 10mm. Inner layer copper 17um (0.5 oz) or 35um (1 oz). Order form also offers OSP finish, 2.5mm thickness, and min castellated hole 0.60mm. Drill tolerance plated 0.1mm, non-plated 0.05mm. Outline tolerance plus or minus 0.20mm. Min silkscreen text height 0.8mm.+# +# Sources:+# - https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1524mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1524mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.3mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/elecrow-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Elecrow",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1524,+ "minClearanceMm": 0.1524,+ "minViaDrillMm": 0.3,+ "minViaDiameterMm": null,+ "minHoleMm": 0.3,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": null,+ "annularRingViaMm": null,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/elecrow-4L.kicad_druadded+35@@ -0,0 +1,35 @@+(version 1)++# Elecrow 4-layer design rules (standard process)+# +# Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil+# Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)+# Min drill: 0.3 mm (11.81 mil)+# Min via: 0.3 mm hole+# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+# Copper weight options: 1 oz, 2 oz+# Surface finishes: HASL, HASL Lead Free, ENIG+# Max board size: 550 x 550 mm+# +# Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. 4 layer adds two inner layers (G1, G2 gerbers). Inner layer copper 17um (0.5 oz) or 35um (1 oz).+# +# Sources:+# - https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1524mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1524mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.3mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/elecrow-6L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Elecrow",+ "process": "standard",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1524,+ "minClearanceMm": 0.1524,+ "minViaDrillMm": 0.3,+ "minViaDiameterMm": null,+ "minHoleMm": 0.3,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": null,+ "annularRingViaMm": null,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/elecrow-6L.kicad_druadded+35@@ -0,0 +1,35 @@+(version 1)++# Elecrow 6-layer design rules (standard process)+# +# Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil+# Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)+# Min drill: 0.3 mm (11.81 mil)+# Min via: 0.3 mm hole+# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+# Copper weight options: 1 oz, 2 oz+# Surface finishes: HASL, HASL Lead Free, ENIG+# Max board size: 550 x 550 mm+# +# Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. Inner layer copper 17um (0.5 oz) or 35um (1 oz).+# +# Sources:+# - https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1524mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1524mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.3mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/eurocircuits-2L.board-setup.jsonadded+33@@ -0,0 +1,33 @@+{+ "vendor": "Eurocircuits",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1,+ "minClearanceMm": 0.1,+ "minViaDrillMm": 0.1,+ "minViaDiameterMm": 0.4,+ "minHoleMm": 0.1,+ "copperEdgeClearanceMm": 0.25,+ "holeToHoleMm": 0.25,+ "annularRingViaMm": 0.125,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1,+ "maskExpansionMm": 0.03+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/standard-pool/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/eurocircuits-2L.kicad_druadded+48@@ -0,0 +1,48 @@+(version 1)++# Eurocircuits 2-layer design rules (standard process)+# +# Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)+# Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); pattern class table: class 6 track/gap 0.150 mm (5.9055 mil), class 7 0.125 mm (4.9213 mil), class 8 0.100 mm (3.937 mil), class 9 0.090 mm (3.5433 mil), class 5 0.175 mm (6.8898 mil)+# Min drill: 0.1 mm (3.94 mil)+# Min via: 0.1 mm hole / 0.4 mm pad+# Annular ring: via 0.125 mm+# Copper to board edge: 0.25 mm+# Hole to hole: 0.25 mm+# Board thickness options: 1.0 mm, 1.55 mm, 2.4 mm+# Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz+# Surface finishes: ENIG, LF HAL, Immersion Silver+# Max board size: 580 x 425 mm+# +# Min board 5 x 5 mm. Base copper foil pooling 2 layer: 12 µm (0.33 oz), 18 µm (0.5 oz), 35 µm (1 oz), 70 µm (2 oz); inner layers 18 µm and 35 µm. Minimum pad diameter: outer PTH finished hole plus 0.300 mm, outer NPTH plus 0.200 mm, inner PTH plus 0.350 mm, inner NPTH plus 0.250 mm. Classification min pattern values also limited by base copper foil: 12 µm 0.090 mm (3.5 mil), 18 µm 0.100 mm (4 mil), 35 µm 0.125 mm (5 mil), 70 µm 0.200 mm (8 mil), 105 µm 0.250 mm (10 mil), for both outer and inner layers. Drill class minimum TOOLSIZE: class A 0.60 mm (23.622 mil), B 0.45 mm (17.7165 mil), C 0.35 mm (13.7795 mil), D 0.25 mm (9.8425 mil), E 0.20 mm (7.874 mil); max board thickness per drill class: A and B 3.20 mm, C 2.40 mm, D 2.00 mm, E 1.60 mm; aspect ratio 1:8. TOOLSIZE equals finished PTH size plus 0.10 mm (4 mil). Soldermask colors pooling: green, blue, black, white, red; non-pooling transparent. Legend white one or both sides, non-pooling black and white.+# +# Sources:+# - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)+# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)+# - https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.25mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/eurocircuits-4L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "Eurocircuits",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1,+ "minClearanceMm": 0.1,+ "minViaDrillMm": 0.1,+ "minViaDiameterMm": 0.4,+ "minHoleMm": 0.1,+ "copperEdgeClearanceMm": 0.25,+ "holeToHoleMm": 0.25,+ "annularRingViaMm": 0.125,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1,+ "maskExpansionMm": 0.03+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/standard-pool/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/eurocircuits-4L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# Eurocircuits 4-layer design rules (standard process)+# +# Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); inner layer same classification values+# Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); pattern class 6 is 0.150 mm (5.9055 mil)+# Min drill: 0.1 mm (3.94 mil)+# Min via: 0.1 mm hole / 0.4 mm pad+# Annular ring: via 0.125 mm+# Copper to board edge: 0.25 mm+# Hole to hole: 0.25 mm+# Board thickness options: 1.0 mm, 1.55 mm+# Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz+# Surface finishes: ENIG, LF HAL, Immersion Silver+# Max board size: 500 x 425 mm+# +# 4 layer pooling board thickness 1.00 mm; 1.55 mm pooling for 6 to 16 layers. Multilayer max dimension 500 x 425 mm. Standard buildups pooled, 8 predefined non-pooling builds; blind and buried vias non-pooling specials. Base copper inner layers pooling 18 µm and 35 µm.+# +# Sources:+# - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)+# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.25mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/eurocircuits-6L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Eurocircuits",+ "process": "standard",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1,+ "minClearanceMm": 0.1,+ "minViaDrillMm": 0.1,+ "minViaDiameterMm": 0.4,+ "minHoleMm": 0.1,+ "copperEdgeClearanceMm": 0.25,+ "holeToHoleMm": 0.25,+ "annularRingViaMm": 0.125,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1,+ "maskExpansionMm": 0.03+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/standard-pool/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/eurocircuits-6L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# Eurocircuits 6-layer design rules (standard process)+# +# Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)+# Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)+# Min drill: 0.1 mm (3.94 mil)+# Min via: 0.1 mm hole / 0.4 mm pad+# Annular ring: via 0.125 mm+# Copper to board edge: 0.25 mm+# Hole to hole: 0.25 mm+# Board thickness options: 1.55 mm+# Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz+# Surface finishes: ENIG, LF HAL, Immersion Silver+# Max board size: 500 x 425 mm+# +# 6 and 8 layers pooling in STANDARD pool; 10 to 16 layers non-pooling. Pooling board thickness for multilayers 6 layers and above is 1.55 mm. Same pattern and drill classification system applies.+# +# Sources:+# - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.25mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/eurocircuits-proto-2L.board-setup.jsonadded+49@@ -0,0 +1,49 @@+{+ "vendor": "Eurocircuits",+ "process": "proto",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.15,+ "minClearanceMm": 0.15,+ "minViaDrillMm": 0.25,+ "minViaDiameterMm": 0.6,+ "minHoleMm": 0.25,+ "copperEdgeClearanceMm": 0.25,+ "holeToHoleMm": 0.25,+ "annularRingViaMm": 0.125,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1,+ "maskExpansionMm": 0.03+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/pcb-proto/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/drilled-holes/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/soldermask/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/legend-print/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/copper-layers/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/eurocircuits-proto-2L.kicad_druadded+52@@ -0,0 +1,52 @@+(version 1)++# Eurocircuits 2-layer design rules (proto process)+# +# Min trace width: 0.15 mm (5.91 mil) - all services, pattern class 6+# Min spacing: 0.15 mm (5.91 mil) - track to track, pattern class 6; class 5 is 0.175 mm (6.8898 mil), class 7 is 0.125 mm (4.9213 mil)+# Min drill: 0.25 mm (9.84 mil)+# Min via: 0.25 mm hole / 0.6 mm pad+# Annular ring: via 0.125 mm+# Copper to board edge: 0.25 mm+# Hole to hole: 0.25 mm+# Board thickness options: 1.55 mm+# Copper weight options: 0.5 oz, 1 oz+# Surface finishes: ENIG, LF HAL+# Max board size: 580 x 425 mm+# +# Min board 20 x 20 mm. Base copper foil: outer layers 18 µm (0.5 oz), inner layers 35 µm (1 oz). Minimum pad diameter: PTH is finished hole plus 0.350 mm on outer and inner layers, NPTH is finished hole plus 0.250 mm. Tool size equals finished PTH hole size plus 0.10 mm (4 mil), NPTH tool size equals finished size. Drill bits in 0.05 mm increments. Standard PTH hole tolerance plus/minus 0.10 mm (0.20 mm range) for holes 4 mm or less, NPTH plus/minus 0.05 mm. Holes with finished size 0.45 mm or smaller are defined as via holes. Pattern class 5 (all services): track/gap 0.175 mm (6.8898 mil), OAR/IAR 0.150 mm (5.9055 mil), IPI 0.225 mm (8.8583 mil). Legend to board edge: 0.250 mm routing, 0.450 mm scoring. Soldermask design rules LDI: pad to pad 0.135 mm (5.315 mil), track to pad 0.090 mm (3.5433 mil); PI colors: pad to pad 0.330 mm (12.9921 mil), track to pad 0.190 mm (7.4803 mil). Mask overlap clearance MOC: LDI 0.060 mm (2.3622 mil), PI 0.090 mm (3.5433 mil).+# +# Sources:+# - https://www.eurocircuits.com/services/pcb-proto/ (read 2026-09-03)+# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)+# - https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png (read 2026-09-03)+# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/drilled-holes/ (read 2026-09-03)+# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/soldermask/ (read 2026-09-03)+# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/legend-print/ (read 2026-09-03)+# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/copper-layers/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.15mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.15mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.25mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.6mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.25mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/eurocircuits-proto-4L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "Eurocircuits",+ "process": "proto",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.15,+ "minClearanceMm": 0.15,+ "minViaDrillMm": 0.25,+ "minViaDiameterMm": 0.6,+ "minHoleMm": 0.25,+ "copperEdgeClearanceMm": 0.25,+ "holeToHoleMm": 0.25,+ "annularRingViaMm": 0.125,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1,+ "maskExpansionMm": 0.03+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/pcb-proto/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/eurocircuits-proto-4L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# Eurocircuits 4-layer design rules (proto process)+# +# Min trace width: 0.15 mm (5.91 mil) - outer and inner layers, pattern class 6+# Min spacing: 0.15 mm (5.91 mil) - pattern class 6; class 5 is 0.175 mm (6.8898 mil)+# Min drill: 0.25 mm (9.84 mil)+# Min via: 0.25 mm hole / 0.6 mm pad+# Annular ring: via 0.125 mm+# Copper to board edge: 0.25 mm+# Hole to hole: 0.25 mm+# Board thickness options: 1.55 mm+# Copper weight options: 0.5 oz, 1 oz+# Surface finishes: ENIG, LF HAL+# Max board size: 500 x 425 mm+# +# 4 layer max board size 500 x 425 mm. Same build parameters as 2 layer. Blind and buried vias not available in PCB proto.+# +# Sources:+# - https://www.eurocircuits.com/services/pcb-proto/ (read 2026-09-03)+# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.15mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.15mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.25mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.6mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.25mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/jlcpcb-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "JLCPCB",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1,+ "minClearanceMm": 0.1,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.25,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.2,+ "annularRingViaMm": 0.18,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://jlcpcb.com/capabilities/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/jlcpcb-2L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# JLCPCB 2-layer design rules (standard process)+# +# Min trace width: 0.1 mm (4.0 mil) - 1 oz copper outer layer+# Min spacing: 0.1 mm (4.0 mil) - 1 oz copper, different nets+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.18 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.2 mm+# Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+# Copper weight options: 1 oz, 2 oz, 2.5 oz, 3.5 oz, 4.5 oz+# Surface finishes: HASL leaded, HASL lead-free, ENIG+# Max board size: 670 x 600 mm+# +# 2 oz: min trace/spacing 0.16/0.16 mm (6.5/6.5 mil). 2.5 oz: 0.2/0.2 mm (8/8 mil). 3.5 oz: 0.25/0.25 mm (10/10 mil). 4.5 oz: 0.3/0.3 mm (12/12 mil). Min drill 0.15 mm costs more. Via diameter should be 0.1 mm (0.15 mm preferred) larger than via hole, preferred min via hole 0.2 mm. PTH annular ring 2 oz: 0.254 mm or above. NPTH pad annular ring 0.45 mm recommended. Min NPTH 0.5 mm. Min plated slot width 0.5 mm. Pad to track clearance 0.1 mm. SMD pad to pad clearance different nets 0.15 mm. Via hole to track 0.2 mm, PTH to track 0.28 mm (0.35 recommended), NPTH to track 0.2 mm. Same-net track spacing 0.25 mm. Min silk text height 1.0 mm (40 mil). Soldermask opening to neighboring trace clearance 0.09 mm. Trace width tolerance plus/minus 20 percent.+# +# Sources:+# - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.25mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/jlcpcb-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "JLCPCB",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.09,+ "minClearanceMm": 0.09,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.25,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.2,+ "annularRingViaMm": 0.15,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://jlcpcb.com/capabilities/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/jlcpcb-4L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# JLCPCB 4-layer design rules (standard process)+# +# Min trace width: 0.09 mm (3.5 mil) - 1 oz copper outer layer, 3 mil acceptable in BGA fan-outs+# Min spacing: 0.09 mm (3.5 mil) - 1 oz copper, different nets+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.15 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.2 mm+# Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+# Copper weight options: 1 oz, 2 oz+# Surface finishes: HASL leaded, HASL lead-free, ENIG+# Max board size: 663 x 593 mm+# +# Same source page as 2 layer, multilayer column. Inner layer copper 0.5/1/2 oz, 0.5 oz default. Inner layer via hole to copper clearance 0.2 mm, inner PTH pad hole to copper clearance 0.3 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Min plated slot width 0.35 mm multilayer. Controlled impedance available. Blind/buried vias not supported, through holes only.+# +# Sources:+# - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.09mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.09mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.25mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/jlcpcb-6L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "JLCPCB",+ "process": "standard",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.09,+ "minClearanceMm": 0.09,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.25,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.2,+ "annularRingViaMm": 0.15,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://jlcpcb.com/capabilities/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/jlcpcb-6L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# JLCPCB 6-layer design rules (standard process)+# +# Min trace width: 0.09 mm (3.5 mil) - 1 oz copper outer layer, 3 mil acceptable in BGA fan-outs+# Min spacing: 0.09 mm (3.5 mil) - 1 oz copper, different nets+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.25 mm pad+# Annular ring: via 0.15 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.2 mm+# Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm+# Copper weight options: 1 oz, 2 oz+# Surface finishes: ENIG+# Max board size: 656 x 586 mm+# +# Same source page as 2 layer, multilayer column. 6 layer and above boards only have ENIG surface finish. Via-in-pad epoxy filled and capped is the default process for 6 layer and above boards, compatible with via diameters 0.15 to 0.55 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Backdrill supported on 4 to 32 layer FR4, thickness 0.8 mm or more.+# +# Sources:+# - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.09mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.09mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.25mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/macrofab-2L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "MacroFab",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.127,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.3048,+ "minViaDiameterMm": null,+ "minHoleMm": 0.3048,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": null,+ "annularRingViaMm": null,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://support.macrofab.com/s/article/pcb-specifications-and-drc",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://support.macrofab.com/s/article/can-i-customize-my-pcb",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/macrofab-2L.kicad_druadded+31@@ -0,0 +1,31 @@+(version 1)++# MacroFab 2-layer design rules (standard process)+# +# Min trace width: 0.127 mm (5.0 mil) - standard manufacturing specifications+# Min spacing: 0.127 mm (5.0 mil) - standard manufacturing specifications+# Min drill: 0.3048 mm (12.0 mil)+# Min via: 0.3048 mm hole+# Board thickness options: 1.6 mm+# Copper weight options: 0.5 oz, 1 oz+# Surface finishes: ENIG+# Max board size: 378.46 x 378.46 mm+# +# Standard (default, non-extended) manufacturing specifications per MacroFab help article: minimum trace width 5 mil, minimum drill 12 mil; page notes the standard tier was later reduced (5 mil spacing, 10 mil drill announced December 2018) but the help article body was only visible via search index, not fully readable on load.+# +# Sources:+# - https://support.macrofab.com/s/article/pcb-specifications-and-drc (read 2026-09-03)+# - https://support.macrofab.com/s/article/can-i-customize-my-pcb (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.127mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.3048mm))+ (condition "A.type == 'pad' || A.type == 'via'"))
kicad/macrofab-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "MacroFab",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.127,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.3048,+ "minViaDiameterMm": null,+ "minHoleMm": 0.3048,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": null,+ "annularRingViaMm": null,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://support.macrofab.com/s/article/pcb-specifications-and-drc",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/macrofab-4L.kicad_druadded+30@@ -0,0 +1,30 @@+(version 1)++# MacroFab 4-layer design rules (standard process)+# +# Min trace width: 0.127 mm (5.0 mil) - standard manufacturing specifications+# Min spacing: 0.127 mm (5.0 mil) - standard manufacturing specifications+# Min drill: 0.3048 mm (12.0 mil)+# Min via: 0.3048 mm hole+# Board thickness options: 1.6 mm+# Copper weight options: 0.5 oz, 1 oz+# Surface finishes: ENIG+# Max board size: 378.46 x 378.46 mm+# +# Same standard specifications as 2-layer; help article does not differentiate by layer count.+# +# Sources:+# - https://support.macrofab.com/s/article/pcb-specifications-and-drc (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.127mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.3048mm))+ (condition "A.type == 'pad' || A.type == 'via'"))
kicad/macrofab-extended-2L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "MacroFab",+ "process": "extended",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0762,+ "minClearanceMm": 0.0762,+ "minViaDrillMm": 0.1016,+ "minViaDiameterMm": 0.254,+ "minHoleMm": 0.1016,+ "copperEdgeClearanceMm": 0.0762,+ "holeToHoleMm": 0.1524,+ "annularRingViaMm": 0.0762,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.127,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.macrofab.com/capabilities/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.macrofab.com/pcba/specs/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/macrofab-extended-2L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# MacroFab 2-layer design rules (extended process)+# +# Min trace width: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper+# Min spacing: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper+# Min drill: 0.1016 mm (4.0 mil)+# Min via: 0.1016 mm hole / 0.254 mm pad+# Annular ring: via 0.0762 mm+# Copper to board edge: 0.0762 mm+# Hole to hole: 0.1524 mm+# Board thickness options: 1.6 mm+# Copper weight options: 0.5 oz, 1 oz+# Surface finishes: ENIG+# Max board size: 378.46 x 378.46 mm+# +# Extended DRC minimums as published. Board thickness 1.6 mm standard, other custom thicknesses supported; thickness tolerance T below 1.0 mm plus minus 15 percent, 1.0 to 1.6 mm plus minus 10 percent, T at or above 1.6 mm plus minus 10 percent. Min via pad derived from published min drill plus 2x annular ring: 4 mil plus 6 mil. NPTH hole size tolerance plus minus 0.05 mm, PTH plus minus 0.08 mm. Board edge tolerance plus minus 0.15 mm. Extended option disabled for 2 oz copper. Paste aperture min 0.1524 mm, paste clearance 0.1524 mm. Silkscreen text height min 0.8 mm.+# +# Sources:+# - https://www.macrofab.com/capabilities/ (read 2026-09-03)+# - https://www.macrofab.com/pcba/specs/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0762mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0762mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1016mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.254mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.0762mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.127mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/macrofab-extended-4L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "MacroFab",+ "process": "extended",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0762,+ "minClearanceMm": 0.0762,+ "minViaDrillMm": 0.1016,+ "minViaDiameterMm": 0.254,+ "minHoleMm": 0.1016,+ "copperEdgeClearanceMm": 0.0762,+ "holeToHoleMm": 0.1524,+ "annularRingViaMm": 0.0762,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.127,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.macrofab.com/capabilities/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.macrofab.com/pcba/specs/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/macrofab-extended-4L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# MacroFab 4-layer design rules (extended process)+# +# Min trace width: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper+# Min spacing: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper+# Min drill: 0.1016 mm (4.0 mil)+# Min via: 0.1016 mm hole / 0.254 mm pad+# Annular ring: via 0.0762 mm+# Copper to board edge: 0.0762 mm+# Hole to hole: 0.1524 mm+# Board thickness options: 1.6 mm+# Copper weight options: 0.5 oz, 1 oz+# Surface finishes: ENIG+# Max board size: 378.46 x 378.46 mm+# +# Same extended DRC table published for all layer counts; MacroFab supports 2 to 36 layer boards per capabilities page. 2 oz copper requires larger trace, spacing, annular ring and disables the extended option; specific 2 oz numbers not published on the read pages.+# +# Sources:+# - https://www.macrofab.com/capabilities/ (read 2026-09-03)+# - https://www.macrofab.com/pcba/specs/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0762mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0762mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1016mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.254mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.0762mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.127mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/nextpcb-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "NextPCB",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0635,+ "minClearanceMm": 0.0762,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.3278,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.3048,+ "annularRingViaMm": 0.0889,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.0762,+ "maskExpansionMm": 0.0381+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.nextpcb.com/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/nextpcb-2L.kicad_druadded+45@@ -0,0 +1,45 @@+(version 1)++# NextPCB 2-layer design rules (standard process)+# +# Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper+# Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.2 mm hole / 0.3278 mm pad+# Annular ring: via 0.0889 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.3048 mm+# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm+# Copper weight options: 0.5 oz, 1 oz, 2 oz+# Max board size: 1500 x 600 mm+# +# Trace/spacing table is by copper weight, not layer count: 0.5oz inner 2.5mil width/3mil spacing, 1oz outer 3mil/3mil, 2oz outer 5.5mil/5.5mil. Annular ring: 3.5mil for 1oz, 4.5mil for 2oz. Min drill 0.15mm only for board thickness 1.2mm or less. PTH hole size 0.2mm or larger single side. Copper to V-cut line 0.4mm (15.748mil). Hole to hole different nets 12mil for CAF avoidance; via to via same net 8mil (0.2032mm); PTH to track 9mil (0.2286mm); NPTH to track 8mil (0.2032mm); SMD pad to track 4mil (0.1016mm); SMD pad to SMD pad 0.15mm; pad to pad with hole different nets 0.40mm. Mask sliver (solder bridge dam): green 3.5mil, black/white 5mil (0.127mm), other colors 4mil (0.1016mm). Silk line width: silkscreen printing 5mil (0.127mm), printer printing 3mil (0.0762mm). Finished copper outer 1oz/2oz, inner 0.5oz/1oz/2oz. Surface finish cell left blank on page. BGA 1oz: min pad 0.2mm, min pad distance 0.15mm. Layer count 1 to 32 supported.+# +# Sources:+# - https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0635mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0762mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.3278mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.0762mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/nextpcb-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "NextPCB",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0635,+ "minClearanceMm": 0.0762,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.3278,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.3048,+ "annularRingViaMm": 0.0889,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.0762,+ "maskExpansionMm": 0.0381+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.nextpcb.com/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/nextpcb-4L.kicad_druadded+45@@ -0,0 +1,45 @@+(version 1)++# NextPCB 4-layer design rules (standard process)+# +# Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper+# Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.2 mm hole / 0.3278 mm pad+# Annular ring: via 0.0889 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.3048 mm+# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm+# Copper weight options: 0.5 oz, 1 oz, 2 oz+# Max board size: 1500 x 500 mm+# +# Same published limits as 2 layer except max dimension 1500x500mm for 4 layers. Trace/spacing by copper weight: 0.5oz inner 2.5mil/3mil, 1oz outer 3mil/3mil, 2oz outer 5.5mil/5.5mil.+# +# Sources:+# - https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0635mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0762mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.3278mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.0762mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/nextpcb-6L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "NextPCB",+ "process": "standard",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0635,+ "minClearanceMm": 0.0762,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.3278,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.3048,+ "annularRingViaMm": 0.0889,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.0762,+ "maskExpansionMm": 0.0381+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.nextpcb.com/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/nextpcb-6L.kicad_druadded+45@@ -0,0 +1,45 @@+(version 1)++# NextPCB 6-layer design rules (standard process)+# +# Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper+# Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.2 mm hole / 0.3278 mm pad+# Annular ring: via 0.0889 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.3048 mm+# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm+# Copper weight options: 0.5 oz, 1 oz, 2 oz+# Max board size: 500 x 400 mm+# +# Max dimension 500x400mm applies to 6 or more layers. Other limits as 2 layer entry.+# +# Sources:+# - https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0635mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0762mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.3278mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.0762mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/nextpcb-advanced-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "NextPCB",+ "process": "advanced",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0635,+ "minClearanceMm": 0.0635,+ "minViaDrillMm": 0.075,+ "minViaDiameterMm": null,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": null,+ "annularRingViaMm": null,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.nextpcb.com/advanced-pcb-manufacturing-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/nextpcb-advanced-2L.kicad_druadded+28@@ -0,0 +1,28 @@+(version 1)++# NextPCB 2-layer design rules (advanced process)+# +# Min trace width: 0.0635 mm (2.5 mil) - FR4 complex designs, general advanced+# Min spacing: 0.0635 mm (2.5 mil) - FR4 complex designs, general advanced+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.075 mm hole+# Surface finishes: HASL, Lead Free HASL, ENIG, OSP, Hard Gold, Electrolytic Gold, Gold Fingers, Immersion Tin, Immersion Silver, ENEPIG+# Max board size: 500 x 600 mm+# +# Up to 32 layers, HDI III and any-layer HDI (ELIC). Trace/space by technology: HDI 2.0mil/2.0mil (0.0508mm), heavy copper 3oz 8mil/8mil (0.2032mm), FPC advanced 1.5mil/1.5mil (0.0381mm). Min laser drill microvia 0.075mm, microvia aspect ratio 0.8:1 to 1:1. Min mechanical drill 0.15mm quoted for rigid-flex. Copper up to 10oz outer (heavy copper section) and 4 to 6oz inner; summary banner states up to 6oz outer/4oz inner. Max board size 500x600mm quoted for high-Tg boards. Rigid-flex up to 20 rigid layers plus 8 flex layers. High-speed boards up to 40 layers. Drill aspect ratio up to 20:1. 0.15mm min drill also on rigid-flex section.+# +# Sources:+# - https://www.nextpcb.com/advanced-pcb-manufacturing-capabilities (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0635mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0635mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))
kicad/osh-park-2L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "OSH Park",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1524,+ "minClearanceMm": 0.1524,+ "minViaDrillMm": 0.254,+ "minViaDiameterMm": 0.508,+ "minHoleMm": 0.254,+ "copperEdgeClearanceMm": 0.381,+ "holeToHoleMm": 0.127,+ "annularRingViaMm": 0.127,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.127,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://docs.oshpark.com/services/two-layer/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://docs.oshpark.com/services/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/osh-park-2L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# OSH Park 2-layer design rules (standard process)+# +# Min trace width: 0.1524 mm (6.0 mil) - 1oz copper+# Min spacing: 0.1524 mm (6.0 mil) - 1oz copper+# Min drill: 0.254 mm (10.0 mil)+# Min via: 0.254 mm hole / 0.508 mm pad+# Annular ring: via 0.127 mm+# Copper to board edge: 0.381 mm+# Hole to hole: 0.127 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# Surface finishes: ENIG+# Max board size: 406.4 x 558.8 mm+# +# Soldermask SMOBC purple both sides. Maximum soldermask alignment 3 mil (0.0762mm) covering retraction, expansion, and shift. Minimum board size 0.25in (6.35mm) square. Maximum soldermask web 4 mil is the minimum web, listed under maskSliver. Substrate 175Tg FR4. Via pad diameter not published. Minimum slot size 20 mil (0.508mm) drill slot only. Blind, buried, and filled+plated vias not supported.+# +# Sources:+# - https://docs.oshpark.com/services/two-layer/ (read 2026-09-03)+# - https://docs.oshpark.com/services/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1524mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1524mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.254mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.508mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.381mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.127mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/osh-park-2oz-0.8mm-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "OSH Park",+ "process": "2oz-0.8mm",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1524,+ "minClearanceMm": 0.1524,+ "minViaDrillMm": 0.254,+ "minViaDiameterMm": 0.508,+ "minHoleMm": 0.254,+ "copperEdgeClearanceMm": 0.381,+ "holeToHoleMm": 0.127,+ "annularRingViaMm": 0.127,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.127,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://docs.oshpark.com/services/two-layer-hhdc/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/osh-park-2oz-0.8mm-2L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# OSH Park 2-layer design rules (2oz-0.8mm process)+# +# Min trace width: 0.1524 mm (6.0 mil) - 2oz copper+# Min spacing: 0.1524 mm (6.0 mil) - 2oz copper+# Min drill: 0.254 mm (10.0 mil)+# Min via: 0.254 mm hole / 0.508 mm pad+# Annular ring: via 0.127 mm+# Copper to board edge: 0.381 mm+# Hole to hole: 0.127 mm+# Board thickness options: 0.8 mm+# Copper weight options: 2 oz+# Surface finishes: ENIG+# Max board size: 406.4 x 558.8 mm+# +# 0.032in (0.8mm) thick PCB with 2oz (2.8 mil, 70um) copper, 180Tg FR4 (Ventec VT-47). Minimum board size 0.25in (6.35mm) square.+# +# Sources:+# - https://docs.oshpark.com/services/two-layer-hhdc/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1524mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1524mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.254mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.508mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.381mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.127mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/osh-park-4L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "OSH Park",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.127,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.254,+ "minViaDiameterMm": 0.4572,+ "minHoleMm": 0.254,+ "copperEdgeClearanceMm": 0.381,+ "holeToHoleMm": 0.127,+ "annularRingViaMm": 0.1016,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.127,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://docs.oshpark.com/services/four-layer/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://docs.oshpark.com/services/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/osh-park-4L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# OSH Park 4-layer design rules (standard process)+# +# Min trace width: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper+# Min spacing: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper+# Min drill: 0.254 mm (10.0 mil)+# Min via: 0.254 mm hole / 0.4572 mm pad+# Annular ring: via 0.1016 mm+# Copper to board edge: 0.381 mm+# Hole to hole: 0.127 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# Surface finishes: ENIG+# Max board size: 406.4 x 558.8 mm+# +# Copper weight is 1oz outer, 0.5oz inner. Plated drill to internal layer copper clearance 10 mil (0.254mm). Substrate 190Tg FR408-HR. Blind and buried vias not supported. Minimum board size 0.25in (6.35mm) square. Via pad diameter not published.+# +# Sources:+# - https://docs.oshpark.com/services/four-layer/ (read 2026-09-03)+# - https://docs.oshpark.com/services/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.127mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.254mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4572mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.381mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.127mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/osh-park-6L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "OSH Park",+ "process": "standard",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.127,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.2032,+ "minViaDiameterMm": 0.4064,+ "minHoleMm": 0.2032,+ "copperEdgeClearanceMm": 0.381,+ "holeToHoleMm": 0.127,+ "annularRingViaMm": 0.1016,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.127,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://docs.oshpark.com/services/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/osh-park-6L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# OSH Park 6-layer design rules (standard process)+# +# Min trace width: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper+# Min spacing: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper+# Min drill: 0.2032 mm (8.0 mil)+# Min via: 0.2032 mm hole / 0.4064 mm pad+# Annular ring: via 0.1016 mm+# Copper to board edge: 0.381 mm+# Hole to hole: 0.127 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# Surface finishes: ENIG+# Max board size: 406.4 x 558.8 mm+# +# Summary values from the services index page. Blind and buried vias not supported.+# +# Sources:+# - https://docs.oshpark.com/services/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.127mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.2032mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4064mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.381mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.127mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/osh-park-after-dark-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "OSH Park",+ "process": "after-dark",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1524,+ "minClearanceMm": 0.1524,+ "minViaDrillMm": 0.254,+ "minViaDiameterMm": 0.508,+ "minHoleMm": 0.254,+ "copperEdgeClearanceMm": 0.381,+ "holeToHoleMm": 0.127,+ "annularRingViaMm": 0.127,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.127,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://docs.oshpark.com/services/afterdark/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/osh-park-after-dark-2L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# OSH Park 2-layer design rules (after-dark process)+# +# Min trace width: 0.1524 mm (6.0 mil) - 1oz copper+# Min spacing: 0.1524 mm (6.0 mil) - 1oz copper+# Min drill: 0.254 mm (10.0 mil)+# Min via: 0.254 mm hole / 0.508 mm pad+# Annular ring: via 0.127 mm+# Copper to board edge: 0.381 mm+# Hole to hole: 0.127 mm+# Board thickness options: 1.6 mm+# Copper weight options: 1 oz+# Surface finishes: ENIG+# Max board size: 406.4 x 558.8 mm+# +# Clear soldermask on black 180Tg FR4 (Ventec VT 447 b), opaque light blocking. Same copper and drill rules as standard 2 layer. Minimum board size 0.25in (6.35mm) square.+# +# Sources:+# - https://docs.oshpark.com/services/afterdark/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1524mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1524mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.254mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.508mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.381mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.127mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/osh-park-flex-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "OSH Park",+ "process": "flex",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1524,+ "minClearanceMm": 0.1524,+ "minViaDrillMm": 0.254,+ "minViaDiameterMm": 0.508,+ "minHoleMm": 0.254,+ "copperEdgeClearanceMm": 0.1524,+ "holeToHoleMm": 0.127,+ "annularRingViaMm": 0.127,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.127,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://docs.oshpark.com/services/flex/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/osh-park-flex-2L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# OSH Park 2-layer design rules (flex process)+# +# Min trace width: 0.1524 mm (6.0 mil) - 1oz copper+# Min spacing: 0.1524 mm (6.0 mil) - 1oz copper+# Min drill: 0.254 mm (10.0 mil)+# Min via: 0.254 mm hole / 0.508 mm pad+# Annular ring: via 0.127 mm+# Copper to board edge: 0.1524 mm+# Hole to hole: 0.127 mm+# Board thickness options: 0.1016 mm+# Copper weight options: 1 oz+# Surface finishes: ENIG+# Max board size: 406.4 x 254 mm+# +# Service temporarily suspended. Panasonic Felios polyimide, 4 mil (0.1016mm) core, clear soldermask. Recommended minimum flex strip width 250 mil (6.35mm). Minimum board size 0.25in (6.35mm) square.+# +# Sources:+# - https://docs.oshpark.com/services/flex/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1524mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1524mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.254mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.508mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.1524mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.127mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/pcbway-2L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "PCBWay",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.454,+ "minHoleMm": 0.2,+ "copperEdgeClearanceMm": 0.25,+ "holeToHoleMm": 0.2794,+ "annularRingViaMm": 0.127,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0508+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.pcbway.com/capabilities.html",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://m.pcbway.com/capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/pcbway-2L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# PCBWay 2-layer design rules (standard process)+# +# Min trace width: 0.1016 mm (4.0 mil) - prototype process, any copper weight; per copper weight outer layer limits are 0.5oz: 4/5mil, 1oz: 5/6mil, 2oz: 7/8mil, 3oz: 10/12mil (before compensation)+# Min spacing: 0.1016 mm (4.0 mil) - prototype process, different nets; per copper weight outer layer limits are 0.5oz: 4/5mil, 1oz: 5/6mil, 2oz: 7/8mil, 3oz: 10/12mil (before compensation)+# Min drill: 0.2 mm (7.87 mil)+# Min via: 0.2 mm hole / 0.454 mm pad+# Annular ring: via 0.127 mm+# Copper to board edge: 0.25 mm+# Hole to hole: 0.2794 mm+# Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+# Copper weight options: 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz+# Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin+# Max board size: 508 x 610 mm+# +# Min board thickness 0.3mm, max board thickness 3.2mm. Prototype quote page lists max PCB size 500x1100mm and drill range 0.2 to 6.3mm. Grid trace 1oz: 9/11mil. Hole diameter tolerance PTH: plus or minus 0.075mm. Panel size max 20x24 inch.+# +# Sources:+# - https://www.pcbway.com/capabilities.html (read 2026-09-03)+# - https://m.pcbway.com/capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.2mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.454mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.25mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/pcbway-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "PCBWay",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.454,+ "minHoleMm": 0.2,+ "copperEdgeClearanceMm": 0.25,+ "holeToHoleMm": 0.2794,+ "annularRingViaMm": 0.127,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0508+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.pcbway.com/capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/pcbway-4L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# PCBWay 4-layer design rules (standard process)+# +# Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 0.5oz: 4mil, 2oz: 6mil, 3oz: 8mil. Outer layer 1oz: 5mil+# Min spacing: 0.127 mm (5.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 0.5oz: 5mil (4/4mil class), 2oz: 8mil, 3oz: 11mil. Outer layer 1oz: 6mil+# Min drill: 0.2 mm (7.87 mil)+# Min via: 0.2 mm hole / 0.454 mm pad+# Annular ring: via 0.127 mm+# Copper to board edge: 0.25 mm+# Hole to hole: 0.2794 mm+# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+# Copper weight options: 0.5 oz, 1 oz, 1.5 oz, 2 oz, 3 oz, 4 oz+# Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin+# Max board size: 508 x 600 mm+# +# Min board thickness 0.6mm, max board thickness 3.2mm. Min inner layer isolation ring (hole to inner layer conductor, before compensation) 7mil (0.1778mm). Inner layer copper weight options 1oz or 1.5oz. Max aspect ratio 8:1.+# +# Sources:+# - https://www.pcbway.com/capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.2mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.454mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.25mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/pcbway-6L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "PCBWay",+ "process": "standard",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.454,+ "minHoleMm": 0.2,+ "copperEdgeClearanceMm": 0.25,+ "holeToHoleMm": 0.2794,+ "annularRingViaMm": 0.127,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0508+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.pcbway.com/capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/pcbway-6L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# PCBWay 6-layer design rules (standard process)+# +# Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1oz (35um) copper, before compensation; outer layer 1oz: 5mil+# Min spacing: 0.127 mm (5.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 2oz: 8mil, 3oz: 11mil. Outer layer 1oz: 6mil+# Min drill: 0.2 mm (7.87 mil)+# Min via: 0.2 mm hole / 0.454 mm pad+# Annular ring: via 0.127 mm+# Copper to board edge: 0.25 mm+# Hole to hole: 0.2794 mm+# Board thickness options: 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+# Copper weight options: 0.5 oz, 1 oz, 1.5 oz, 2 oz, 3 oz, 4 oz+# Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin+# Max board size: 508 x 600 mm+# +# Min board thickness 0.9mm, max board thickness 3.2mm. Min inner layer isolation ring (hole to inner layer conductor, before compensation) 8mil (0.2032mm). Inner layer copper weight options 1oz or 1.5oz. Max aspect ratio 8:1.+# +# Sources:+# - https://www.pcbway.com/capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.2mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.454mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.25mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/pcbway-advanced-2L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "PCBWay",+ "process": "advanced",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0508,+ "minClearanceMm": 0.0508,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.3024,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.3556,+ "annularRingViaMm": 0.0762,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0381+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.pcbway.com/advanced-pcb-capabilities.html",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.pcbway.com/capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/pcbway-advanced-2L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# PCBWay 2-layer design rules (advanced process)+# +# Min trace width: 0.0508 mm (2.0 mil) - outer layer, 1/3 oz base copper, only part of traces on the board, not whole board; capabilities table advanced outer 0.5oz: 4mil with parts 3.5mil (0.0889mm) in BGA chip area+# Min spacing: 0.0508 mm (2.0 mil) - outer layer, 1/3 oz base copper, partial traces only; capabilities table advanced outer 0.5oz: 4mil, parts 3.5mil+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.3024 mm pad+# Annular ring: via 0.0762 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.3556 mm+# Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+# Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz+# Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver+# Max board size: 609 x 889 mm+# +# Advanced page does not distinguish limits by layer count for 2 layers. Min board thickness 0.25mm. Max aspect ratio 20:1. Max layer count 64. Min BGA pad diameter 8mil, min BGA pitch 0.4mm. Min base copper 1/3 oz, max finished copper 8 oz. Min insulating layer thickness 2mil. Max board thickness 4.5mm.+# +# Sources:+# - https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03)+# - https://www.pcbway.com/capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0508mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0508mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.3024mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/pcbway-advanced-4L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "PCBWay",+ "process": "advanced",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0508,+ "minClearanceMm": 0.0508,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.3024,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.3556,+ "annularRingViaMm": 0.0762,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0381+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.pcbway.com/advanced-pcb-capabilities.html",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.pcbway.com/capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/pcbway-advanced-4L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# PCBWay 4-layer design rules (advanced process)+# +# Min trace width: 0.0508 mm (2.0 mil) - inner layer 2/2mil with H/H oz base copper (partial traces only); capabilities table advanced inner 0.5oz: 4mil, parts 3.5mil. Outer layer 2/2mil with 1/3 oz base copper+# Min spacing: 0.0508 mm (2.0 mil) - inner layer H/H oz or outer 1/3 oz base copper, partial traces only; capabilities table advanced inner 0.5oz: 3.5mil spacing (4/3.5mil), outer 0.5oz: 4mil+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.3024 mm pad+# Annular ring: via 0.0762 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.3556 mm+# Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+# Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz+# Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver+# Max board size: 609 x 889 mm+# +# Advanced page does not distinguish limits by layer count; same published values apply to 4 layers. Min board thickness 0.4mm (advanced), standard 0.6mm. Min inner layer isolation ring advanced 6mil (0.1524mm) before compensation. Max aspect ratio 20:1. HDI 1 to 7 steps. Max board thickness 4.5mm.+# +# Sources:+# - https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03)+# - https://www.pcbway.com/capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0508mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0508mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.3024mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/pcbway-advanced-6L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "PCBWay",+ "process": "advanced",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.0508,+ "minClearanceMm": 0.0508,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.3024,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.2,+ "holeToHoleMm": 0.3556,+ "annularRingViaMm": 0.0762,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.15,+ "maskExpansionMm": 0.0381+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.pcbway.com/advanced-pcb-capabilities.html",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.pcbway.com/capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/pcbway-advanced-6L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# PCBWay 6-layer design rules (advanced process)+# +# Min trace width: 0.0508 mm (2.0 mil) - inner layer 2/2mil with H/H oz base copper (partial traces only); capabilities table advanced inner 0.5oz: 4mil, parts 3.5mil. Outer layer 2/2mil with 1/3 oz base copper+# Min spacing: 0.0508 mm (2.0 mil) - inner layer H/H oz or outer 1/3 oz base copper, partial traces only; capabilities table advanced inner 0.5oz: 3.5mil spacing, outer 0.5oz: 4mil+# Min drill: 0.15 mm (5.91 mil)+# Min via: 0.15 mm hole / 0.3024 mm pad+# Annular ring: via 0.0762 mm+# Copper to board edge: 0.2 mm+# Hole to hole: 0.3556 mm+# Board thickness options: 0.7 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm+# Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz+# Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver+# Max board size: 609 x 889 mm+# +# Advanced page does not distinguish limits by layer count; same published values apply to 6 layers. Min board thickness 0.7mm (advanced), standard 0.9mm. Min inner layer isolation ring advanced 6.5mil (0.1651mm) before compensation. Max aspect ratio 20:1. HDI 1 to 7 steps. Max board thickness 4.5mm.+# +# Sources:+# - https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03)+# - https://www.pcbway.com/capabilities.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.0508mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.0508mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.3024mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.2mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.15mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/seeed-fusion-2L.board-setup.jsonadded+29@@ -0,0 +1,29 @@+{+ "vendor": "Seeed Fusion",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.4,+ "minHoleMm": 0.2,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": 0.3,+ "annularRingViaMm": 0.1,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1016,+ "maskExpansionMm": 0.1+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.seeedstudio.com/fusion_pcb.html",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/seeed-fusion-2L.kicad_druadded+47@@ -0,0 +1,47 @@+(version 1)++# Seeed Fusion 2-layer design rules (standard process)+# +# Min trace width: 0.1016 mm (4.0 mil) - 1 oz copper, 4/4 mil option+# Min spacing: 0.1016 mm (4.0 mil) - 1 oz copper, 4/4 mil option+# Min drill: 0.2 mm (7.87 mil)+# Min via: 0.2 mm hole / 0.4 mm pad+# Annular ring: via 0.1 mm+# Copper to board edge: 0.3 mm+# Hole to hole: 0.3 mm+# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm+# Copper weight options: 1 oz, 2 oz, 3 oz+# Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold+# Max board size: 500 x 500 mm+# +# Trace width/spacing by copper weight: 1 oz: 4/4, 5/5, or 6/6 mil options (0.1016/0.127/0.1524 mm); 2 oz: 10/10 mil (0.254 mm); 3 oz: 15/15 mil (0.381 mm). RF coil designs require 6/6 mil but select 4/4 mil option. Min board size 10 x 10 mm. Drill ranges: NPTH 0.2 to 6.3 mm, PTH 0.2 to 5.8 mm, via holes 0.2 to 0.5 mm (vias 0.3 mm and smaller guarantee full mask tenting). Min via pad not published directly, min annular ring 0.1 mm implies pad = drill + 0.2 mm. Min plated slot 0.65 mm, non-plated slot 0.8 mm. BGA pitch guidance: 0.45 mm pitch with 6/6 mil, 0.35 mm with 5/5 mil, 0.25 mm with 4/4 mil.+# +# Sources:+# - https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)+# - https://www.seeedstudio.com/fusion_pcb.html (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.2mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1016mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/seeed-fusion-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Seeed Fusion",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.4,+ "minHoleMm": 0.2,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": 0.3,+ "annularRingViaMm": 0.1,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1016,+ "maskExpansionMm": 0.1+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/seeed-fusion-4L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# Seeed Fusion 4-layer design rules (standard process)+# +# Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option+# Min spacing: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option+# Min drill: 0.2 mm (7.87 mil)+# Min via: 0.2 mm hole / 0.4 mm pad+# Annular ring: via 0.1 mm+# Copper to board edge: 0.3 mm+# Hole to hole: 0.3 mm+# Board thickness options: 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm+# Copper weight options: 1 oz, 2 oz, 3 oz+# Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold+# Max board size: 500 x 500 mm+# +# Minimum trace width in inner layers for 4 layer boards: 0.15 mm (6 mil). Inner layer base copper 0.017 mm (0.5 oz), outer 0.035 to 0.07 mm (1 to 2 oz). Same trace width/spacing options by copper weight as 2 layer: 1 oz 4/4, 5/5, 6/6 mil; 2 oz 10/10 mil; 3 oz 15/15 mil. Min board size 10 x 10 mm. Castellated holes (plated half-holes) min 0.50 mm.+# +# Sources:+# - https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.2mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1016mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/seeed-fusion-6L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Seeed Fusion",+ "process": "standard",+ "layerCount": 6,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.2,+ "minViaDiameterMm": 0.4,+ "minHoleMm": 0.2,+ "copperEdgeClearanceMm": 0.3,+ "holeToHoleMm": 0.3,+ "annularRingViaMm": 0.1,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": 0.1016,+ "maskExpansionMm": 0.1+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/seeed-fusion-6L.kicad_druadded+46@@ -0,0 +1,46 @@+(version 1)++# Seeed Fusion 6-layer design rules (standard process)+# +# Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option+# Min spacing: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option+# Min drill: 0.2 mm (7.87 mil)+# Min via: 0.2 mm hole / 0.4 mm pad+# Annular ring: via 0.1 mm+# Copper to board edge: 0.3 mm+# Hole to hole: 0.3 mm+# Board thickness options: 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm+# Copper weight options: 1 oz, 2 oz, 3 oz+# Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold+# Max board size: 500 x 500 mm+# +# Seeed standard service supports 1 to 6 layers (layers table extends to 16). Board thickness options listed are for 6 and 8 layer boards. Inner layer trace width limit not separately published for 6 layer; 4 layer value is 0.15 mm (6 mil).+# +# Sources:+# - https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.2mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.3mm))+ (condition "A.type == 'track'"))++(rule "min-silk-thickness"+ (constraint text_thickness (min 0.1016mm))+ (layer "*.SilkS")+ (condition "A.type == 'text' || A.type == 'graphic'"))
kicad/seeed-fusion-advanced-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Seeed Fusion",+ "process": "advanced",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.127,+ "minClearanceMm": 0.127,+ "minViaDrillMm": 0.1,+ "minViaDiameterMm": 0.3032,+ "minHoleMm": 0.1,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": 0.2286,+ "annularRingViaMm": 0.1016,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": 0.08+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/seeed-fusion-advanced-2L.kicad_druadded+35@@ -0,0 +1,35 @@+(version 1)++# Seeed Fusion 2-layer design rules (advanced process)+# +# Min trace width: 0.127 mm (5.0 mil) - outer layer, 1 oz copper+# Min spacing: 0.127 mm (5.0 mil) - outer layer, 1 oz copper+# Min drill: 0.1 mm (3.94 mil)+# Min via: 0.1 mm hole / 0.3032 mm pad+# Annular ring: via 0.1016 mm+# Hole to hole: 0.2286 mm+# Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+# Surface finishes: HASL, HASL lead-free, ENIG, Hard Gold, Immersion Tin, Immersion Silver, OSP+# Max board size: n/a x n/a mm+# +# Outer layer trace/spacing by copper weight: 1/3 oz 3/3 mil (0.0762 mm), 0.5 oz 4/4 mil (0.1016 mm), 1 oz 5/5 mil (0.127 mm), 2 oz 6/8 mil (0.1524/0.2032 mm), 3 oz 7/10 mil (0.1778/0.254 mm), 4 oz 8/13 mil (0.2032/0.3302 mm), 5 oz 10/16 mil (0.254/0.4064 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). Board thickness rigid 0.2 to 8.0 mm. Min castellated hole diameter 0.35 mm. Plugged vias finished diameter 0.15 to 0.8 mm. HDI stacks 1+n+1, 1+1+n+1+1, 2+n+2. Outline, V-cut and milling slot tolerance 0.10 mm. Solder mask colors include purple, matte green, customized. Board size limits not published on this page.+# +# Sources:+# - https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.127mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.127mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.3032mm))+ (condition "A.type == 'via'"))
kicad/seeed-fusion-advanced-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Seeed Fusion",+ "process": "advanced",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.1,+ "minViaDiameterMm": 0.3032,+ "minHoleMm": 0.1,+ "copperEdgeClearanceMm": null,+ "holeToHoleMm": 0.2286,+ "annularRingViaMm": 0.1016,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": 0.08+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/seeed-fusion-advanced-4L.kicad_druadded+35@@ -0,0 +1,35 @@+(version 1)++# Seeed Fusion 4-layer design rules (advanced process)+# +# Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1 oz copper+# Min spacing: 0.1016 mm (4.0 mil) - inner layer, 1 oz copper+# Min drill: 0.1 mm (3.94 mil)+# Min via: 0.1 mm hole / 0.3032 mm pad+# Annular ring: via 0.1016 mm+# Hole to hole: 0.2286 mm+# Copper weight options: 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz+# Surface finishes: HASL, HASL lead-free, ENIG, Hard Gold, Immersion Tin, Immersion Silver, OSP+# Max board size: n/a x n/a mm+# +# Inner layer trace/spacing by copper weight: 0.5 oz 3/3 mil (0.0762 mm), 1 oz 4/4 mil (0.1016 mm), 2 oz 5/6 mil (0.127/0.1524 mm), 3 oz 7/9 mil (0.1778/0.2286 mm), 4 oz 8/12 mil (0.2032/0.3048 mm), 5 oz 10/15 mil (0.254/0.381 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). For outer layer values see the 2 layer entry. FR4 1 to 30 layers, rigid-flex up to 36 rigid layers, board thickness rigid 0.2 to 8.0 mm. Back drilling diameter 0.5 to 6.3 mm, depth tolerance 0.10 mm. Min BGA pad diameter 7 mil (0.1778 mm) with 4/4 mil trace/spacing.+# +# Sources:+# - https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.1mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.3032mm))+ (condition "A.type == 'via'"))
kicad/sierra-circuits-2L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Sierra Circuits",+ "process": "standard",+ "layerCount": 2,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.4547,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.254,+ "holeToHoleMm": null,+ "annularRingViaMm": 0.0254,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.protoexpress.com/products/rigid-pcb/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/sierra-circuits-2L.kicad_druadded+40@@ -0,0 +1,40 @@+(version 1)++# Sierra Circuits 2-layer design rules (standard process)+# +# Min trace width: 0.1016 mm (4.0 mil) - STANDARD tier+# Min spacing: 0.1016 mm (4.0 mil) - STANDARD tier+# Min drill: 0.15 mm (5.9 mil)+# Min via: 0.15 mm hole / 0.4547 mm pad+# Annular ring: via 0.0254 mm+# Copper to board edge: 0.254 mm+# Board thickness options: 0.254 mm, 7.62 mm+# Copper weight options: 4 oz+# Surface finishes: HASL, Lead-Free HASL, OSP (Shikoku F2), OSP (Entek), ENIG, Immersion Silver, Electrolytic Soft Gold, Electrolytic Hard Gold, Selective Gold+# Max board size: 304.8 x 457.2 mm+# +# Values from the rigid PCB STANDARD tier table, published per process tier, not broken out by layer count, so 2-layer uses the same STANDARD values. Min board thickness 0.010 in (0.254 mm), max 0.300 in (7.62 mm). Max finished copper: outer layer 4 oz, inner layer 4 oz, min starting foil 3 microns. Min via pad derived from published process pad formula D plus 0.012 in, i.e. min drill 5.9 mil plus 12 mil. Annular ring 1 mil as stated in the process pad row. Max panel size STANDARD tier 12 x 18 in. Smallest laser drill 5 mil (0.127 mm), min finished hole 4 mil (0.102 mm). Solder mask registration 2 mil (0.0508 mm), solder mask feature tolerance 1.5 mil (0.0381 mm).+# +# Sources:+# - https://www.protoexpress.com/products/rigid-pcb/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4547mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.254mm))+ (condition "A.type == 'track'"))
kicad/sierra-circuits-4L.board-setup.jsonadded+25@@ -0,0 +1,25 @@+{+ "vendor": "Sierra Circuits",+ "process": "standard",+ "layerCount": 4,+ "boardSetupConstraints": {+ "minTrackWidthMm": 0.1016,+ "minClearanceMm": 0.1016,+ "minViaDrillMm": 0.15,+ "minViaDiameterMm": 0.4547,+ "minHoleMm": 0.15,+ "copperEdgeClearanceMm": 0.254,+ "holeToHoleMm": null,+ "annularRingViaMm": 0.0254,+ "annularRingPadMm": null,+ "silkMinLineWidthMm": null,+ "maskExpansionMm": null+ },+ "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",+ "sources": [+ {+ "url": "https://www.protoexpress.com/products/rigid-pcb/",+ "dateRead": "2026-09-03"+ }+ ]+}
kicad/sierra-circuits-4L.kicad_druadded+40@@ -0,0 +1,40 @@+(version 1)++# Sierra Circuits 4-layer design rules (standard process)+# +# Min trace width: 0.1016 mm (4.0 mil) - STANDARD tier+# Min spacing: 0.1016 mm (4.0 mil) - STANDARD tier+# Min drill: 0.15 mm (5.9 mil)+# Min via: 0.15 mm hole / 0.4547 mm pad+# Annular ring: via 0.0254 mm+# Copper to board edge: 0.254 mm+# Board thickness options: 0.254 mm, 7.62 mm+# Copper weight options: 4 oz+# Surface finishes: HASL, Lead-Free HASL, OSP (Shikoku F2), OSP (Entek), ENIG, Immersion Silver, Electrolytic Soft Gold, Electrolytic Hard Gold, Selective Gold+# Max board size: 304.8 x 457.2 mm+# +# Same STANDARD tier table as 2-layer, Sierra does not publish separate 4-layer limits on this page. Blind and buried vias available. Controlled impedance tolerance 10 percent STANDARD tier.+# +# Sources:+# - https://www.protoexpress.com/products/rigid-pcb/ (read 2026-09-03)++(rule "min-track-width"+ (constraint track_width (min 0.1016mm))+ (layer "*.Cu")+ (condition "A.type == 'track'"))++(rule "min-clearance"+ (constraint clearance (min 0.1016mm))+ (condition "A.type == 'track' && B.type == 'track'"))++(rule "min-hole"+ (constraint hole (min 0.15mm))+ (condition "A.type == 'pad' || A.type == 'via'"))++(rule "min-via-diameter"+ (constraint via_diameter (min 0.4547mm))+ (condition "A.type == 'via'"))++(rule "min-edge-clearance"+ (constraint edge_clearance (min 0.254mm))+ (condition "A.type == 'track'"))
page.json+43−4@@ -14,14 +14,53 @@ "name": "John Lauer", "email": "[email protected]" },- "tags": [],+ "tags": [+ "pcb",+ "design-rules",+ "drc",+ "fabrication",+ "jlcpcb",+ "pcbway",+ "instapcb",+ "fusion",+ "kicad",+ "altium",+ "edru",+ "kicad_dru"+ ], "license": "proprietary", "visibility": { "public": true },- "sample_prompts": [],- "discovery_triggers": [],- "discovery_pitch": null,+ "sample_prompts": [+ {+ "label": "Compare fab limits",+ "prompt": "what is the minimum trace width and drill for JLCPCB vs PCBWay 2 layer?"+ },+ {+ "label": "Load rules into Fusion",+ "prompt": "load the JLCPCB 4 layer design rules into my Fusion board"+ },+ {+ "label": "KiCad rules for a fab",+ "prompt": "give me the KiCad custom rules file for OSH Park 2 layer"+ }+ ],+ "discovery_triggers": [+ "design rules",+ "DRC",+ "JLCPCB rules",+ "load PCBWay rules",+ "InstaPCB rules",+ "drc load",+ "fab capabilities",+ "min trace width",+ "min drill size",+ "annular ring",+ "edru",+ "kicad_dru"+ ],+ "discovery_pitch": "Use when the user asks about PCB design rules, DRC limits, fab capabilities, minimum trace width, drill, via or annular ring limits, or wants to load a fab's rules into Fusion, KiCad or Altium.", "metadata": {}, "created_at": "2026-09-03T12:39:44.118Z", "updated_at": "2026-09-03T12:39:44.118Z",
rules/index.jsonadded+1267@@ -0,0 +1,1267 @@+{+ "generatedBy": "tools/generate.py",+ "unitNote": "mm primary, mil secondary (1 mil = 0.0254 mm)",+ "vendors": [+ {+ "vendor": "Adom InstaPCB",+ "vendorSlug": "adom-instapcb",+ "process": "standard",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/adom-instapcb.json",+ "fusionEdru": "fusion/adom-instapcb-2L.edru",+ "fusionDru": "fusion/adom-instapcb-2L.dru",+ "kicadDru": "kicad/adom-instapcb-2L.kicad_dru",+ "kicadBoardSetup": "kicad/adom-instapcb-2L.board-setup.json",+ "altiumRul": "altium/adom-instapcb-2L.RUL"+ },+ "sources": [+ {+ "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru",+ "dateRead": "2026-09-03",+ "kind": "bundled-house-rule-file"+ }+ ]+ },+ {+ "vendor": "Adom InstaPCB",+ "vendorSlug": "adom-instapcb",+ "process": "standard",+ "layerCount": 4,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/adom-instapcb.json",+ "fusionEdru": "fusion/adom-instapcb-4L.edru",+ "fusionDru": "fusion/adom-instapcb-4L.dru",+ "kicadDru": "kicad/adom-instapcb-4L.kicad_dru",+ "kicadBoardSetup": "kicad/adom-instapcb-4L.board-setup.json",+ "altiumRul": "altium/adom-instapcb-4L.RUL"+ },+ "sources": [+ {+ "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru",+ "dateRead": "2026-09-03",+ "kind": "bundled-house-rule-file"+ }+ ]+ },+ {+ "vendor": "Advanced Circuits (4PCB)",+ "vendorSlug": "advanced-circuits-4pcb",+ "process": "standard",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/advanced-circuits-4pcb.json",+ "fusionEdru": "fusion/advanced-circuits-4pcb-2L.edru",+ "fusionDru": "fusion/advanced-circuits-4pcb-2L.dru",+ "kicadDru": "kicad/advanced-circuits-4pcb-2L.kicad_dru",+ "kicadBoardSetup": "kicad/advanced-circuits-4pcb-2L.board-setup.json",+ "altiumRul": "altium/advanced-circuits-4pcb-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.4pcb.com/laminate-material-vendors.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Advanced Circuits (4PCB)",+ "vendorSlug": "advanced-circuits-4pcb",+ "process": "standard",+ "layerCount": 4,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/advanced-circuits-4pcb.json",+ "fusionEdru": "fusion/advanced-circuits-4pcb-4L.edru",+ "fusionDru": "fusion/advanced-circuits-4pcb-4L.dru",+ "kicadDru": "kicad/advanced-circuits-4pcb-4L.kicad_dru",+ "kicadBoardSetup": "kicad/advanced-circuits-4pcb-4L.board-setup.json",+ "altiumRul": "altium/advanced-circuits-4pcb-4L.RUL"+ },+ "sources": [+ {+ "url": "https://www.4pcb.com/laminate-material-vendors.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Advanced Circuits (4PCB)",+ "vendorSlug": "advanced-circuits-4pcb",+ "process": "advanced-standard",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/advanced-circuits-4pcb.json",+ "fusionEdru": "fusion/advanced-circuits-4pcb-advanced-standard-2L.edru",+ "fusionDru": "fusion/advanced-circuits-4pcb-advanced-standard-2L.dru",+ "kicadDru": "kicad/advanced-circuits-4pcb-advanced-standard-2L.kicad_dru",+ "kicadBoardSetup": "kicad/advanced-circuits-4pcb-advanced-standard-2L.board-setup.json",+ "altiumRul": "altium/advanced-circuits-4pcb-advanced-standard-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Advanced Circuits (4PCB)",+ "vendorSlug": "advanced-circuits-4pcb",+ "process": "advanced-standard",+ "layerCount": 4,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/advanced-circuits-4pcb.json",+ "fusionEdru": "fusion/advanced-circuits-4pcb-advanced-standard-4L.edru",+ "fusionDru": "fusion/advanced-circuits-4pcb-advanced-standard-4L.dru",+ "kicadDru": "kicad/advanced-circuits-4pcb-advanced-standard-4L.kicad_dru",+ "kicadBoardSetup": "kicad/advanced-circuits-4pcb-advanced-standard-4L.board-setup.json",+ "altiumRul": "altium/advanced-circuits-4pcb-advanced-standard-4L.RUL"+ },+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Advanced Circuits (4PCB)",+ "vendorSlug": "advanced-circuits-4pcb",+ "process": "advanced",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/advanced-circuits-4pcb.json",+ "fusionEdru": "fusion/advanced-circuits-4pcb-advanced-2L.edru",+ "fusionDru": "fusion/advanced-circuits-4pcb-advanced-2L.dru",+ "kicadDru": "kicad/advanced-circuits-4pcb-advanced-2L.kicad_dru",+ "kicadBoardSetup": "kicad/advanced-circuits-4pcb-advanced-2L.board-setup.json",+ "altiumRul": "altium/advanced-circuits-4pcb-advanced-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Advanced Circuits (4PCB)",+ "vendorSlug": "advanced-circuits-4pcb",+ "process": "advanced",+ "layerCount": 4,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/advanced-circuits-4pcb.json",+ "fusionEdru": "fusion/advanced-circuits-4pcb-advanced-4L.edru",+ "fusionDru": "fusion/advanced-circuits-4pcb-advanced-4L.dru",+ "kicadDru": "kicad/advanced-circuits-4pcb-advanced-4L.kicad_dru",+ "kicadBoardSetup": "kicad/advanced-circuits-4pcb-advanced-4L.board-setup.json",+ "altiumRul": "altium/advanced-circuits-4pcb-advanced-4L.RUL"+ },+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Advanced Circuits (4PCB)",+ "vendorSlug": "advanced-circuits-4pcb",+ "process": "development-npi",+ "layerCount": 2,+ "filesGenerated": false,+ "files": {+ "record": "rules/records/advanced-circuits-4pcb.json",+ "fusionEdru": "fusion/advanced-circuits-4pcb-development-npi-2L.edru",+ "fusionDru": "fusion/advanced-circuits-4pcb-development-npi-2L.dru",+ "kicadDru": "kicad/advanced-circuits-4pcb-development-npi-2L.kicad_dru",+ "kicadBoardSetup": "kicad/advanced-circuits-4pcb-development-npi-2L.board-setup.json",+ "altiumRul": "altium/advanced-circuits-4pcb-development-npi-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ],+ "note": "No generated rule files: the vendor does not publish one or more of min trace width, min spacing, min drill for this process/layer count."+ },+ {+ "vendor": "Aisler",+ "vendorSlug": "aisler",+ "process": "enig",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/aisler.json",+ "fusionEdru": "fusion/aisler-enig-2L.edru",+ "fusionDru": "fusion/aisler-enig-2L.dru",+ "kicadDru": "kicad/aisler-enig-2L.kicad_dru",+ "kicadBoardSetup": "kicad/aisler-enig-2L.board-setup.json",+ "altiumRul": "altium/aisler-enig-2L.RUL"+ },+ "sources": [+ {+ "url": "https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Aisler",+ "vendorSlug": "aisler",+ "process": "hasl",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/aisler.json",+ "fusionEdru": "fusion/aisler-hasl-2L.edru",+ "fusionDru": "fusion/aisler-hasl-2L.dru",+ "kicadDru": "kicad/aisler-hasl-2L.kicad_dru",+ "kicadBoardSetup": "kicad/aisler-hasl-2L.board-setup.json",+ "altiumRul": "altium/aisler-hasl-2L.RUL"+ },+ "sources": [+ {+ "url": "https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Aisler",+ "vendorSlug": "aisler",+ "process": "enig",+ "layerCount": 4,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/aisler.json",+ "fusionEdru": "fusion/aisler-enig-4L.edru",+ "fusionDru": "fusion/aisler-enig-4L.dru",+ "kicadDru": "kicad/aisler-enig-4L.kicad_dru",+ "kicadBoardSetup": "kicad/aisler-enig-4L.board-setup.json",+ "altiumRul": "altium/aisler-enig-4L.RUL"+ },+ "sources": [+ {+ "url": "https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "ALLPCB",+ "vendorSlug": "allpcb",+ "process": "standard",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/allpcb.json",+ "fusionEdru": "fusion/allpcb-2L.edru",+ "fusionDru": "fusion/allpcb-2L.dru",+ "kicadDru": "kicad/allpcb-2L.kicad_dru",+ "kicadBoardSetup": "kicad/allpcb-2L.board-setup.json",+ "altiumRul": "altium/allpcb-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.allpcb.com/standard_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "ALLPCB",+ "vendorSlug": "allpcb",+ "process": "advanced",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/allpcb.json",+ "fusionEdru": "fusion/allpcb-advanced-2L.edru",+ "fusionDru": "fusion/allpcb-advanced-2L.dru",+ "kicadDru": "kicad/allpcb-advanced-2L.kicad_dru",+ "kicadBoardSetup": "kicad/allpcb-advanced-2L.board-setup.json",+ "altiumRul": "altium/allpcb-advanced-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "ALLPCB",+ "vendorSlug": "allpcb",+ "process": "advanced",+ "layerCount": 4,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/allpcb.json",+ "fusionEdru": "fusion/allpcb-advanced-4L.edru",+ "fusionDru": "fusion/allpcb-advanced-4L.dru",+ "kicadDru": "kicad/allpcb-advanced-4L.kicad_dru",+ "kicadBoardSetup": "kicad/allpcb-advanced-4L.board-setup.json",+ "altiumRul": "altium/allpcb-advanced-4L.RUL"+ },+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "ALLPCB",+ "vendorSlug": "allpcb",+ "process": "advanced",+ "layerCount": 6,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/allpcb.json",+ "fusionEdru": "fusion/allpcb-advanced-6L.edru",+ "fusionDru": "fusion/allpcb-advanced-6L.dru",+ "kicadDru": "kicad/allpcb-advanced-6L.kicad_dru",+ "kicadBoardSetup": "kicad/allpcb-advanced-6L.board-setup.json",+ "altiumRul": "altium/allpcb-advanced-6L.RUL"+ },+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Elecrow",+ "vendorSlug": "elecrow",+ "process": "standard",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/elecrow.json",+ "fusionEdru": "fusion/elecrow-2L.edru",+ "fusionDru": "fusion/elecrow-2L.dru",+ "kicadDru": "kicad/elecrow-2L.kicad_dru",+ "kicadBoardSetup": "kicad/elecrow-2L.board-setup.json",+ "altiumRul": "altium/elecrow-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Elecrow",+ "vendorSlug": "elecrow",+ "process": "standard",+ "layerCount": 4,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/elecrow.json",+ "fusionEdru": "fusion/elecrow-4L.edru",+ "fusionDru": "fusion/elecrow-4L.dru",+ "kicadDru": "kicad/elecrow-4L.kicad_dru",+ "kicadBoardSetup": "kicad/elecrow-4L.board-setup.json",+ "altiumRul": "altium/elecrow-4L.RUL"+ },+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Elecrow",+ "vendorSlug": "elecrow",+ "process": "standard",+ "layerCount": 6,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/elecrow.json",+ "fusionEdru": "fusion/elecrow-6L.edru",+ "fusionDru": "fusion/elecrow-6L.dru",+ "kicadDru": "kicad/elecrow-6L.kicad_dru",+ "kicadBoardSetup": "kicad/elecrow-6L.board-setup.json",+ "altiumRul": "altium/elecrow-6L.RUL"+ },+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Eurocircuits",+ "vendorSlug": "eurocircuits",+ "process": "proto",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/eurocircuits.json",+ "fusionEdru": "fusion/eurocircuits-proto-2L.edru",+ "fusionDru": "fusion/eurocircuits-proto-2L.dru",+ "kicadDru": "kicad/eurocircuits-proto-2L.kicad_dru",+ "kicadBoardSetup": "kicad/eurocircuits-proto-2L.board-setup.json",+ "altiumRul": "altium/eurocircuits-proto-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/pcb-proto/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/drilled-holes/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/soldermask/",+ "dateRead": "2026-09-03"+ },+ {+ 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"kicad/seeed-fusion-4L.board-setup.json",+ "altiumRul": "altium/seeed-fusion-4L.RUL"+ },+ "sources": [+ {+ "url": "https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Seeed Fusion",+ "vendorSlug": "seeed-fusion",+ "process": "standard",+ "layerCount": 6,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/seeed-fusion.json",+ "fusionEdru": "fusion/seeed-fusion-6L.edru",+ "fusionDru": "fusion/seeed-fusion-6L.dru",+ "kicadDru": "kicad/seeed-fusion-6L.kicad_dru",+ "kicadBoardSetup": "kicad/seeed-fusion-6L.board-setup.json",+ "altiumRul": "altium/seeed-fusion-6L.RUL"+ },+ "sources": [+ {+ "url": "https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Seeed Fusion",+ "vendorSlug": "seeed-fusion",+ "process": "advanced",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/seeed-fusion.json",+ "fusionEdru": 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"https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Sierra Circuits",+ "vendorSlug": "sierra-circuits",+ "process": "standard",+ "layerCount": 2,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/sierra-circuits.json",+ "fusionEdru": "fusion/sierra-circuits-2L.edru",+ "fusionDru": "fusion/sierra-circuits-2L.dru",+ "kicadDru": "kicad/sierra-circuits-2L.kicad_dru",+ "kicadBoardSetup": "kicad/sierra-circuits-2L.board-setup.json",+ "altiumRul": "altium/sierra-circuits-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.protoexpress.com/products/rigid-pcb/",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Sierra Circuits",+ "vendorSlug": "sierra-circuits",+ "process": "standard",+ "layerCount": 4,+ "filesGenerated": true,+ "files": {+ "record": "rules/records/sierra-circuits.json",+ "fusionEdru": "fusion/sierra-circuits-4L.edru",+ "fusionDru": "fusion/sierra-circuits-4L.dru",+ "kicadDru": "kicad/sierra-circuits-4L.kicad_dru",+ "kicadBoardSetup": "kicad/sierra-circuits-4L.board-setup.json",+ "altiumRul": "altium/sierra-circuits-4L.RUL"+ },+ "sources": [+ {+ "url": "https://www.protoexpress.com/products/rigid-pcb/",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "vendor": "Sierra Circuits",+ "vendorSlug": "sierra-circuits",+ "process": "turnkey-pro",+ "layerCount": 2,+ "filesGenerated": false,+ "files": {+ "record": "rules/records/sierra-circuits.json",+ "fusionEdru": "fusion/sierra-circuits-turnkey-pro-2L.edru",+ "fusionDru": "fusion/sierra-circuits-turnkey-pro-2L.dru",+ "kicadDru": "kicad/sierra-circuits-turnkey-pro-2L.kicad_dru",+ "kicadBoardSetup": "kicad/sierra-circuits-turnkey-pro-2L.board-setup.json",+ "altiumRul": "altium/sierra-circuits-turnkey-pro-2L.RUL"+ },+ "sources": [+ {+ "url": "https://www.protoexpress.com/",+ "dateRead": "2026-09-03"+ }+ ],+ "note": "No generated rule files: the vendor does not publish one or more of min trace width, min spacing, min drill for this process/layer count."+ },+ {+ "vendor": "Sierra Circuits",+ "vendorSlug": "sierra-circuits",+ "process": "turnkey-pro",+ "layerCount": 4,+ "filesGenerated": false,+ "files": {+ "record": "rules/records/sierra-circuits.json",+ "fusionEdru": "fusion/sierra-circuits-turnkey-pro-4L.edru",+ "fusionDru": "fusion/sierra-circuits-turnkey-pro-4L.dru",+ "kicadDru": "kicad/sierra-circuits-turnkey-pro-4L.kicad_dru",+ "kicadBoardSetup": "kicad/sierra-circuits-turnkey-pro-4L.board-setup.json",+ "altiumRul": "altium/sierra-circuits-turnkey-pro-4L.RUL"+ },+ "sources": [+ {+ "url": "https://www.protoexpress.com/",+ "dateRead": "2026-09-03"+ }+ ],+ "note": "No generated rule files: the vendor does not publish one or more of min trace width, min spacing, min drill for this process/layer count."+ }+ ]+}
rules/records/adom-instapcb.jsonadded+57@@ -0,0 +1,57 @@+{+ "vendor": "Adom InstaPCB",+ "vendorSlug": "adom-instapcb",+ "vendorUrl": "https://instapcb.com",+ "records": [+ {+ "process": "standard",+ "layerCount": 2,+ "minTraceWidth": {"mm": 0.10, "mil": 3.94, "condition": "1 oz copper"},+ "minSpacing": {"mm": 0.10, "mil": 3.94, "condition": "1 oz copper, different nets"},+ "minDrill": {"mm": 0.15, "mil": 5.91},+ "minVia": {"drillMm": 0.15, "drillMil": 5.91, "padMm": 0.25, "padMil": 9.84},+ "annularRing": {"viaMm": 0.10, "viaMil": 3.94, "padMm": 0.18, "padMil": 7.09, "note": "0.25 mm or above preferred"},+ "copperToBoardEdge": {"mm": 0.20, "mil": 7.87},+ "holeToHole": {"mm": 0.20, "mil": 7.87},+ "maskExpansion": {"mm": 0.038, "mil": 1.50},+ "maskSliver": null,+ "silkLineWidth": null,+ "silkToCopper": null,+ "minCopperClearance": {"mm": 0.10, "mil": 3.94, "condition": "different nets"},+ "boardThicknessOptionsMm": [1.6],+ "copperWeightOptionsOz": [1],+ "surfaceFinishes": [],+ "maxBoardSize": null,+ "drillRange": {"minMm": 0.15, "maxMm": 6.3, "note": "holes with diameter >= 6.3 mm are CNC routed from a smaller drilled hole; min non-plated hole 0.50 mm"},+ "notes": "House baseline of the Adom InstaPCB fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.",+ "sources": [+ {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-house-rule-file"}+ ]+ },+ {+ "process": "standard",+ "layerCount": 4,+ "minTraceWidth": {"mm": 0.09, "mil": 3.54, "condition": "1 oz copper, multilayer"},+ "minSpacing": {"mm": 0.09, "mil": 3.54, "condition": "1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs"},+ "minDrill": {"mm": 0.15, "mil": 5.91},+ "minVia": {"drillMm": 0.15, "drillMil": 5.91, "padMm": 0.25, "padMil": 9.84},+ "annularRing": {"viaMm": 0.10, "viaMil": 3.94, "padMm": 0.18, "padMil": 7.09, "note": "0.25 mm or above preferred"},+ "copperToBoardEdge": {"mm": 0.20, "mil": 7.87},+ "holeToHole": {"mm": 0.20, "mil": 7.87},+ "maskExpansion": {"mm": 0.038, "mil": 1.50},+ "maskSliver": null,+ "silkLineWidth": null,+ "silkToCopper": null,+ "minCopperClearance": {"mm": 0.09, "mil": 3.54, "condition": "different nets"},+ "boardThicknessOptionsMm": [1.6],+ "copperWeightOptionsOz": [1],+ "surfaceFinishes": [],+ "maxBoardSize": null,+ "drillRange": {"minMm": 0.15, "maxMm": 6.3, "note": "holes with diameter >= 6.3 mm are CNC routed from a smaller drilled hole; min non-plated hole 0.50 mm"},+ "notes": "BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias.",+ "sources": [+ {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-house-rule-file"}+ ]+ }+ ]+}
rules/records/advanced-circuits-4pcb.jsonadded+528@@ -0,0 +1,528 @@+{+ "vendor": "Advanced Circuits (4PCB)",+ "vendorSlug": "advanced-circuits-4pcb",+ "vendorUrl": null,+ "records": [+ {+ "process": "standard",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "outer trace, standard spec"+ },+ "minSpacing": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "standard spec trace/space 5/5 mils"+ },+ "minDrill": {+ "mm": 0.254,+ "mil": 10.0+ },+ "minVia": {+ "drillMm": 0.254,+ "drillMil": 10.0,+ "padMm": null,+ "padMil": null+ },+ "annularRing": null,+ "copperToBoardEdge": null,+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": null,+ "silkLineWidth": null,+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 0.7874,+ 1.5748,+ 2.3622,+ 3.175+ ],+ "copperWeightOptionsOz": [+ 1,+ 2+ ],+ "surfaceFinishes": [+ "Lead-Free HAL"+ ],+ "maxBoardSize": {+ "xMm": 406.4,+ "yMm": 558.8+ },+ "notes": "Standard spec: FR-4, 0 to 12 layers, IPC Class 2, quantity 1 to 10000 plus, turn time same day to 5 day. Hole tolerance plus or minus 0.005 in (0.127 mm). Rout tolerance plus or minus 0.010 in (0.254 mm). Solder mask LPI green, legend white. Board thickness options 0.031, 0.062, 0.093, 0.125 in. Standard finish pricing assumes lead-free HAL; ENIG or immersion silver at no extra cost if HAL unavailable. Same spec applies to 2 and 4 layer; page does not differentiate by layer count below 12.",+ "sources": [+ {+ "url": "https://www.4pcb.com/laminate-material-vendors.html",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "standard (Standard Technology PCBs)"+ },+ {+ "process": "standard",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "outer trace, standard spec"+ },+ "minSpacing": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "standard spec trace/space 5/5 mils"+ },+ "minDrill": {+ "mm": 0.254,+ "mil": 10.0+ },+ "minVia": {+ "drillMm": 0.254,+ "drillMil": 10.0,+ "padMm": null,+ "padMil": null+ },+ "annularRing": null,+ "copperToBoardEdge": null,+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": null,+ "silkLineWidth": null,+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 0.7874,+ 1.5748,+ 2.3622,+ 3.175+ ],+ "copperWeightOptionsOz": [+ 1,+ 2+ ],+ "surfaceFinishes": [+ "Lead-Free HAL"+ ],+ "maxBoardSize": {+ "xMm": 406.4,+ "yMm": 558.8+ },+ "notes": "Same standard spec as 2 layer. Typical 4-layer stackup published at 0.020, 0.031, 0.062, 0.093, 0.125 in finished thickness with 1 oz copper, max board size 16 x 22 in for 0.031 to 0.093 in, 14 x 20 in (355.6 x 508 mm) at 0.125 in.",+ "sources": [+ {+ "url": "https://www.4pcb.com/laminate-material-vendors.html",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "standard (Standard Technology PCBs)"+ },+ {+ "process": "advanced-standard",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.1397,+ "mil": 5.5,+ "condition": "outer layer, 1 oz Cu base; other weights: 0.0762 mm (3 mil) at 1/4 and 3/8 oz base, 0.1143 mm (4.5 mil) at 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)"+ },+ "minSpacing": {+ "mm": 0.1397,+ "mil": 5.5,+ "condition": "outer layer trace to trace, 1 oz Cu base; 0.0762 mm (3 mil) at 1/4, 3/8, 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)"+ },+ "minDrill": {+ "mm": 0.1499,+ "mil": 5.9,+ "condition": "smallest mechanical PTH via, aspect ratio driven; smallest component PTH 0.381 mm (15 mil)"+ },+ "minVia": {+ "drillMm": 0.1499,+ "drillMil": 5.9,+ "padMm": 0.5309,+ "padMil": 20.9+ },+ "annularRing": {+ "viaMm": 0.1905,+ "viaMil": 7.5,+ "note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"+ },+ "copperToBoardEdge": {+ "mm": 0.254,+ "mil": 10.0+ },+ "holeToHole": {+ "mm": 0.3048,+ "mil": 12.0,+ "condition": "minimum hole to hole edge for PTH"+ },+ "maskExpansion": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "solder mask clearance to pad, i.e. annular ring"+ },+ "maskSliver": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "solder mask web width over laminate between pads; 0.0762 mm (3 mil) over copper"+ },+ "silkLineWidth": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "minimum, white only, height 15 to 20 mil; standard silkscreen 5 mil width, 25 to 30 mil height"+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.1397,+ "mil": 5.5,+ "condition": "different nets, outer layer 1 oz Cu base"+ },+ "boardThicknessOptionsMm": [],+ "copperWeightOptionsOz": [+ 0.25,+ 0.375,+ 0.5,+ 1,+ 2,+ 3,+ 4+ ],+ "surfaceFinishes": [],+ "maxBoardSize": {+ "xMm": 406.4,+ "yMm": 558.8+ },+ "notes": "Capabilities table is per facility and per tier; this object is Santa Clara, CA, Standard column. Min board thickness 0.01 in (0.254 mm), max board thickness 0.25 in (6.35 mm). PTH tolerance plus or minus 0.003 in (0.0762 mm). Drill to copper for PTH 0.01 in (0.254 mm). Minimum pad 0.015 in (0.381 mm), minimum isolated pad 0.01 in (0.254 mm). Min copper sliver between antipads 0.005 in (0.127 mm). Aspect ratio plated through holes 10:1 for drilled greater than 0.020 in, 10:1 for 0.010 to 0.019 in. Other facilities differ, e.g. Maple Grove MN standard outer 1 oz trace width is 0.1016 mm (4 mil), smallest mech via 0.0043 in (0.1092 mm).",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "advanced capabilities, Santa Clara CA facility, Standard tier"+ },+ {+ "process": "advanced-standard",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.1397,+ "mil": 5.5,+ "condition": "outer layer, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil); inner 1/2 oz: 0.0889 mm (3.5 mil)"+ },+ "minSpacing": {+ "mm": 0.1397,+ "mil": 5.5,+ "condition": "outer layer trace to trace, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil)"+ },+ "minDrill": {+ "mm": 0.1499,+ "mil": 5.9,+ "condition": "smallest mechanical PTH via, aspect ratio driven; smallest component PTH 0.381 mm (15 mil)"+ },+ "minVia": {+ "drillMm": 0.1499,+ "drillMil": 5.9,+ "padMm": 0.5309,+ "padMil": 20.9+ },+ "annularRing": {+ "viaMm": 0.1905,+ "viaMil": 7.5,+ "note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"+ },+ "copperToBoardEdge": {+ "mm": 0.254,+ "mil": 10.0+ },+ "holeToHole": {+ "mm": 0.3048,+ "mil": 12.0,+ "condition": "minimum hole to hole edge for PTH"+ },+ "maskExpansion": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "solder mask clearance to pad, i.e. annular ring"+ },+ "maskSliver": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "solder mask web width over laminate between pads; 0.0762 mm (3 mil) over copper"+ },+ "silkLineWidth": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "minimum, white only, height 15 to 20 mil; standard silkscreen 5 mil width, 25 to 30 mil height"+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.1397,+ "mil": 5.5,+ "condition": "different nets, outer layer 1 oz Cu base"+ },+ "boardThicknessOptionsMm": [],+ "copperWeightOptionsOz": [+ 0.25,+ 0.375,+ 0.5,+ 1,+ 2,+ 3,+ 4+ ],+ "surfaceFinishes": [],+ "maxBoardSize": {+ "xMm": 406.4,+ "yMm": 558.8+ },+ "notes": "Same capabilities table values as 2 layer; buried vias mechanical drill minimum 0.0059 in (0.1499 mm), blind vias mechanical 0.0059 in, laser drilled blind via minimum 0.004 in (0.1016 mm).",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "advanced capabilities, Santa Clara CA facility, Standard tier"+ },+ {+ "process": "advanced",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "outer layer, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz base, 0.0762 mm (3 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz; inner 1 oz: 0.0889 mm (3.5 mil)"+ },+ "minSpacing": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "outer layer trace to trace, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz, 0.0635 mm (2.5 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz"+ },+ "minDrill": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "smallest mechanical PTH via, aspect ratio driven"+ },+ "minVia": {+ "drillMm": 0.127,+ "drillMil": 5.0,+ "padMm": 0.508,+ "padMil": 20.0+ },+ "annularRing": {+ "viaMm": 0.1905,+ "viaMil": 7.5,+ "note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"+ },+ "copperToBoardEdge": {+ "mm": 0.2032,+ "mil": 8.0+ },+ "holeToHole": {+ "mm": 0.254,+ "mil": 10.0,+ "condition": "minimum hole to hole edge for PTH"+ },+ "maskExpansion": {+ "mm": 0.0508,+ "mil": 2.0,+ "condition": "solder mask clearance to pad, i.e. annular ring"+ },+ "maskSliver": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "solder mask web width over laminate between pads; 0.0508 mm (2 mil) over copper"+ },+ "silkLineWidth": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "minimum, white only, height 15 to 20 mil"+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "different nets, outer layer 1 oz Cu base"+ },+ "boardThicknessOptionsMm": [],+ "copperWeightOptionsOz": [+ 0.25,+ 0.375,+ 0.5,+ 1,+ 2,+ 3,+ 4+ ],+ "surfaceFinishes": [],+ "maxBoardSize": {+ "xMm": 482.6,+ "yMm": 558.8+ },+ "notes": "Santa Clara CA, Advanced tier. Max board size 19 x 22 in. Min board thickness 0.008 in (0.2032 mm). PTH tolerance plus or minus 0.002 in (0.0508 mm). Minimum pad 0.01 in (0.254 mm). Min outer layer trace for filled and plated over vias 0.004 in (0.1016 mm). Aspect ratio PTH 12:1.",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "advanced capabilities, Santa Clara CA facility, Advanced tier"+ },+ {+ "process": "advanced",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "outer layer, 1 oz Cu base; inner 1 oz: 0.0889 mm (3.5 mil)"+ },+ "minSpacing": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "outer layer trace to trace, 1 oz Cu base; inner 1 oz: 0.1016 mm (4 mil)"+ },+ "minDrill": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "smallest mechanical PTH via, aspect ratio driven"+ },+ "minVia": {+ "drillMm": 0.127,+ "drillMil": 5.0,+ "padMm": 0.508,+ "padMil": 20.0+ },+ "annularRing": {+ "viaMm": 0.1905,+ "viaMil": 7.5,+ "note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"+ },+ "copperToBoardEdge": {+ "mm": 0.2032,+ "mil": 8.0+ },+ "holeToHole": {+ "mm": 0.254,+ "mil": 10.0,+ "condition": "minimum hole to hole edge for PTH"+ },+ "maskExpansion": {+ "mm": 0.0508,+ "mil": 2.0,+ "condition": "solder mask clearance to pad, i.e. annular ring"+ },+ "maskSliver": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "solder mask web width over laminate between pads; 0.0508 mm (2 mil) over copper"+ },+ "silkLineWidth": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "minimum, white only, height 15 to 20 mil"+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.1016,+ "mil": 4.0,+ "condition": "different nets, outer layer 1 oz Cu base"+ },+ "boardThicknessOptionsMm": [],+ "copperWeightOptionsOz": [+ 0.25,+ 0.375,+ 0.5,+ 1,+ 2,+ 3,+ 4+ ],+ "surfaceFinishes": [],+ "maxBoardSize": {+ "xMm": 482.6,+ "yMm": 558.8+ },+ "notes": "Same Advanced tier values as 2 layer for this facility.",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "advanced capabilities, Santa Clara CA facility, Advanced tier"+ },+ {+ "process": "development-npi",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "outer layer, 1 oz Cu base; 0.0381 mm (1.5 mil) at 1/4 and 3/8 oz base, 0.0559 mm (2.2 mil) at 1/2 oz, 0.1016 mm (4 mil) at 2 oz, 0.1524 mm (6 mil) at 3 oz; inner 1 oz: 0.0762 mm (3 mil)"+ },+ "minSpacing": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "outer layer trace to trace, 1 oz Cu base; 0.0381 mm (1.5 mil) at 1/4 and 3/8 oz, 0.0559 mm (2.2 mil) at 1/2 oz, 0.127 mm (5 mil) at 2 oz, 0.1524 mm (6 mil) at 3 oz"+ },+ "minDrill": null,+ "minVia": null,+ "annularRing": {+ "viaMm": 0.1905,+ "viaMil": 7.5,+ "note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"+ },+ "copperToBoardEdge": {+ "mm": 0.127,+ "mil": 5.0+ },+ "holeToHole": {+ "mm": 0.2032,+ "mil": 8.0,+ "condition": "minimum hole to hole edge for PTH"+ },+ "maskExpansion": {+ "mm": 0.0254,+ "mil": 1.0,+ "condition": "solder mask clearance to pad, i.e. annular ring"+ },+ "maskSliver": {+ "mm": 0.0508,+ "mil": 2.0,+ "condition": "solder mask web width over laminate between pads and over copper"+ },+ "silkLineWidth": null,+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "different nets, outer layer 1 oz Cu base"+ },+ "boardThicknessOptionsMm": [],+ "copperWeightOptionsOz": [+ 0.5,+ 1,+ 2,+ 3+ ],+ "surfaceFinishes": [],+ "maxBoardSize": {+ "xMm": null,+ "yMm": null+ },+ "notes": "Santa Clara CA, Development (NPI) tier; maximum board size not published for this tier. Min board thickness 0.008 in (0.2032 mm). PTH tolerance plus or minus 0.0015 in (0.0381 mm). Minimum pad 0.008 in (0.2032 mm). Min outer layer trace for filled and plated over vias 0.003 in (0.0762 mm). Aspect ratio PTH 14:1. Smallest PTH fillable and plated over 0.005 in (0.127 mm).",+ "sources": [+ {+ "url": "https://www.4pcb.com/pcb-capabilities.html",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "advanced capabilities, Santa Clara CA facility, Development (NPI) tier"+ }+ ]+}
rules/records/aisler.jsonadded+262@@ -0,0 +1,262 @@+{+ "vendor": "Aisler",+ "vendorSlug": "aisler",+ "vendorUrl": null,+ "records": [+ {+ "process": "enig",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "Cu 35um (1oz), ENIG finish"+ },+ "minSpacing": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "Cu 35um (1oz), ENIG finish"+ },+ "minDrill": {+ "mm": 0.25,+ "mil": 10.0,+ "condition": "via drill, drills up to 0.45mm are treated as vias and not adjusted; PTH drills start at 0.5mm"+ },+ "minVia": {+ "drillMm": 0.25,+ "drillMil": 10.0,+ "padMm": 0.45,+ "padMil": 17.72+ },+ "annularRing": {+ "viaMm": 0.1,+ "viaMil": 4.0,+ "note": "via, PTH annular ring 300um (12 mil)"+ },+ "copperToBoardEdge": {+ "mm": 0.3,+ "mil": 12.0+ },+ "holeToHole": {+ "mm": 0.3,+ "mil": 12.0+ },+ "maskExpansion": {+ "mm": 0.05,+ "mil": 2.0,+ "condition": "suggested soldermask expansion"+ },+ "maskSliver": {+ "mm": 0.1,+ "mil": 4.0,+ "condition": "minimum soldermask dam, recommended but not required for ENIG"+ },+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 6.0+ },+ "silkToCopper": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "silkscreen to pad, silkscreen on pads not supported"+ },+ "minCopperClearance": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "different nets, copper to copper"+ },+ "boardThicknessOptionsMm": [+ 1.6+ ],+ "copperWeightOptionsOz": [+ 1+ ],+ "surfaceFinishes": [+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 500.0,+ "yMm": 500.0+ },+ "notes": "Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Min SMD pad size 200um (8 mil). Copper to NPTH clearance 250um (10 mil), copper to NPTH slot clearance 300um (12 mil) for slots under and over 1.8mm. PTH drill range 0.5mm to 5.6mm, PTH annular ring 300um. Via drill range 0.25mm to 0.45mm, via annular ring 100um. NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm, PTH slot annular ring 300um. Min silkscreen text height 800um (32 mil). Max silkscreen coverage 25% per board side. Castellated edges supported free of charge. Green soldermask (Peters Elpemer AS 2467), buried, blind, micro, and tented vias not supported. Via pad diameter not published.",+ "sources": [+ {+ "url": "https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "Beautiful Boards 2 Layer 1.6mm ENIG (35um copper)"+ },+ {+ "process": "hasl",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.2,+ "mil": 8.0,+ "condition": "Cu 35um (1oz), HASL finish"+ },+ "minSpacing": {+ "mm": 0.15,+ "mil": 6.0,+ "condition": "Cu 35um (1oz), HASL finish"+ },+ "minDrill": {+ "mm": 0.3,+ "mil": 12.0,+ "condition": "via drill, PTH drills start at 0.5mm"+ },+ "minVia": {+ "drillMm": 0.3,+ "drillMil": 12.0,+ "padMm": 0.7,+ "padMil": 27.56+ },+ "annularRing": {+ "viaMm": 0.2,+ "viaMil": 8.0,+ "note": "via, 175um absolute minimum to compensate for drill enlargement up to 0.45mm; PTH annular ring 300um (12 mil)"+ },+ "copperToBoardEdge": {+ "mm": 0.3,+ "mil": 12.0+ },+ "holeToHole": {+ "mm": 0.3,+ "mil": 12.0+ },+ "maskExpansion": {+ "mm": 0.05,+ "mil": 2.0,+ "condition": "suggested soldermask expansion"+ },+ "maskSliver": {+ "mm": 0.1,+ "mil": 4.0,+ "condition": "minimum soldermask dam, required for HASL"+ },+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 6.0+ },+ "silkToCopper": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "silkscreen to pad, silkscreen on pads not supported"+ },+ "minCopperClearance": {+ "mm": 0.15,+ "mil": 6.0,+ "condition": "different nets, copper to copper"+ },+ "boardThicknessOptionsMm": [+ 1.6+ ],+ "copperWeightOptionsOz": [+ 1+ ],+ "surfaceFinishes": [+ "HASL"+ ],+ "maxBoardSize": {+ "xMm": 500.0,+ "yMm": 500.0+ },+ "notes": "Lead-free HASL. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Via drill range 0.3mm to 0.45mm, drill may be enlarged up to 0.45mm. PTH drill range 0.5mm to 5.6mm, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges not supported with HASL. Green soldermask (Peters Elpemer AS 2467). Via pad diameter not published.",+ "sources": [+ {+ "url": "https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "Beautiful Boards 2 Layer 1.6mm HASL (35um copper)"+ },+ {+ "process": "enig",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "Cu 35um (1oz), ENIG finish"+ },+ "minSpacing": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "Cu 35um (1oz), ENIG finish"+ },+ "minDrill": {+ "mm": 0.25,+ "mil": 10.0,+ "condition": "via drill, PTH drills start at 0.5mm"+ },+ "minVia": {+ "drillMm": 0.25,+ "drillMil": 10.0,+ "padMm": 0.45,+ "padMil": 17.72+ },+ "annularRing": {+ "viaMm": 0.1,+ "viaMil": 4.0,+ "note": "via, PTH annular ring 300um (12 mil)"+ },+ "copperToBoardEdge": {+ "mm": 0.3,+ "mil": 12.0+ },+ "holeToHole": {+ "mm": 0.3,+ "mil": 12.0+ },+ "maskExpansion": {+ "mm": 0.05,+ "mil": 2.0,+ "condition": "suggested soldermask expansion"+ },+ "maskSliver": {+ "mm": 0.1,+ "mil": 4.0,+ "condition": "minimum soldermask dam, recommended but not required for ENIG"+ },+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 6.0+ },+ "silkToCopper": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "silkscreen to pad, silkscreen on pads not supported"+ },+ "minCopperClearance": {+ "mm": 0.125,+ "mil": 5.0,+ "condition": "different nets, copper to copper"+ },+ "boardThicknessOptionsMm": [+ 0.8,+ 1.6+ ],+ "copperWeightOptionsOz": [+ 1+ ],+ "surfaceFinishes": [+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 500.0,+ "yMm": 500.0+ },+ "notes": "Source page states rules are valid for both 0.8mm and 1.6mm PCB thickness. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. PTH drill range 0.5mm to 5.6mm, via drill range 0.25mm to 0.45mm, via annular ring 100um, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges supported free of charge. Green soldermask. Via pad diameter not published.",+ "sources": [+ {+ "url": "https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "Beautiful Boards 4 Layer ENIG (35um copper, 0.8mm and 1.6mm)"+ }+ ],+ "unreachable": [+ "https://aisler.net/about/manufacturing (404)",+ "https://aisler.net/pages/technical-capabilities (returned login page)",+ "https://aisler.net/capabilities (404)"+ ]+}
rules/records/allpcb.jsonadded+340@@ -0,0 +1,340 @@+{+ "vendor": "ALLPCB",+ "vendorSlug": "allpcb",+ "vendorUrl": null,+ "records": [+ {+ "process": "standard",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "all copper weights; vendor suggests 6mil (0.15mm) or more to save cost"+ },+ "minSpacing": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "all copper weights; vendor suggests 6mil (0.15mm) or more to save cost"+ },+ "minDrill": {+ "mm": 0.2,+ "mil": 7.87+ },+ "minVia": null,+ "annularRing": {+ "viaMm": 0.153,+ "viaMil": 6.02+ },+ "copperToBoardEdge": {+ "mm": 0.3,+ "mil": 11.81+ },+ "holeToHole": {+ "mm": 0.2032,+ "mil": 8.0+ },+ "maskExpansion": null,+ "maskSliver": {+ "mm": 0.1,+ "mil": 3.94+ },+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 5.91+ },+ "silkToCopper": null,+ "minCopperClearance": null,+ "boardThicknessOptionsMm": [+ 0.4,+ 3.2+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 1,+ 2+ ],+ "surfaceFinishes": [+ "HASL",+ "Immersion Gold",+ "Immersion Silver",+ "Immersion Tin",+ "OSP",+ "Hard Gold plating",+ "Soft Gold plating",+ "NiPdAu"+ ],+ "maxBoardSize": {+ "xMm": 506,+ "yMm": 580+ },+ "notes": "Single published limit set covers 1 to 14 layers, so this entry also applies to 4 and 6 layer boards. Board thickness is a continuous 0.4 to 3.2mm range. Copper: outer 1oz to 2oz (35 to 70um), inner 0.5oz to 2oz (18 to 70um). Min dimension 80x80mm. Drill range 0.2 to 6.5mm, finished CNC hole 0.2 to 6.5mm, hole size tolerance \u00b10.075mm. Copper to V-cut line 0.4mm (15.748mil) for panelized boards. Via space same net 8mil (0.2032mm), different nets 17mil (0.4318mm), component vias different nets 24mil (0.6096mm). Annular ring 6mil or larger where surrounded by traces. Min slot width 0.6mm, finished slot 0.45mm for HASL and 0.5mm for other finishes. Board thickness to via diameter ratio 6:1, 7:1 to 8:1 adds a fabrication day. Min character height 0.8mm (31.4961mil), width to height ratio 1:5. Mask sliver recorded from solder mask bridge value 0.1mm (price may rise).",+ "sources": [+ {+ "url": "https://www.allpcb.com/standard_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "process": "advanced",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.076,+ "mil": 3.0,+ "condition": "1oz copper"+ },+ "minSpacing": {+ "mm": 0.076,+ "mil": 3.0,+ "condition": "1oz copper"+ },+ "minDrill": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minVia": {+ "drillMm": 0.2,+ "drillMil": 7.87,+ "padMm": 0.5,+ "padMil": 19.68+ },+ "annularRing": {+ "viaMm": 0.18,+ "viaMil": 7.09+ },+ "copperToBoardEdge": {+ "mm": 0.3,+ "mil": 11.81+ },+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": {+ "mm": 0.075,+ "mil": 2.95+ },+ "silkLineWidth": {+ "mm": 0.1,+ "mil": 3.94+ },+ "silkToCopper": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minCopperClearance": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pad edge to trace edge; BGA pad to trace 0.075mm (2.9528mil)"+ },+ "boardThicknessOptionsMm": [+ 0.4,+ 4.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2,+ 3,+ 4,+ 5,+ 6+ ],+ "surfaceFinishes": [+ "Bare Copper",+ "OSP",+ "HASL With Lead",+ "HASL Lead-free",+ "Immersion Gold",+ "Immersion Tin",+ "Immersion Silver",+ "Nickel Palladium Gold",+ "OSP plus Selective Immersion Gold",+ "Lead-free HASL plus Selective Immersion Gold",+ "Lead-free HASL plus Selective Gold Plating"+ ],+ "maxBoardSize": {+ "xMm": 630,+ "yMm": 520+ },+ "notes": "Double-side board via/pad: 0.2mm inner diameter, 0.5mm outer diameter; outer diameter must be 0.1mm larger than inner, 0.15mm preferred; preferred min via hole 0.2mm. Trace/spacing by copper weight: 1oz 0.076mm, 2oz 0.14mm (5.5118mil), 3oz 0.2mm (7.874mil), 4oz 0.25mm (9.8425mil), 5oz 0.35mm (13.7795mil), 6oz 0.45mm (17.7165mil). Trace width tolerance \u00b120%. Annular ring: plated DIP holes 1oz recommended 0.2mm, limit 0.18mm; non-plated DIP holes recommended 0.4mm (15.748mil). Min plated slot 0.7mm (27.5591mil), min non-plated slot 0.8mm (31.4961mil). Board thickness to min plated hole ratio 10:1. Plated half hole diameter 0.4mm or more, spacing 0.35mm (13.7795mil). Min single PCB size 10x5mm. Copper to board edge 0.3mm at non-stamp-hole panel areas; V-cut line to copper 0.4mm. Mask sliver recorded from min solder bridge width: green 0.075mm, other colors 0.125mm (4.9213mil). Silk text height 0.75mm (29.5276mil). BGA pad diameter 0.2mm or more. Edge rail 4mm or more.",+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "process": "advanced",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.076,+ "mil": 3.0,+ "condition": "1oz copper"+ },+ "minSpacing": {+ "mm": 0.076,+ "mil": 3.0,+ "condition": "1oz copper"+ },+ "minDrill": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minVia": {+ "drillMm": 0.15,+ "drillMil": 5.91,+ "padMm": 0.25,+ "padMil": 9.84+ },+ "annularRing": {+ "viaMm": 0.18,+ "viaMil": 7.09+ },+ "copperToBoardEdge": {+ "mm": 0.3,+ "mil": 11.81+ },+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": {+ "mm": 0.075,+ "mil": 2.95+ },+ "silkLineWidth": {+ "mm": 0.1,+ "mil": 3.94+ },+ "silkToCopper": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minCopperClearance": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pad edge to trace edge; BGA pad to trace 0.075mm (2.9528mil)"+ },+ "boardThicknessOptionsMm": [+ 0.4,+ 4.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2,+ 3,+ 4,+ 5,+ 6+ ],+ "surfaceFinishes": [+ "Bare Copper",+ "OSP",+ "HASL With Lead",+ "HASL Lead-free",+ "Immersion Gold",+ "Immersion Tin",+ "Immersion Silver",+ "Nickel Palladium Gold",+ "OSP plus Selective Immersion Gold",+ "Lead-free HASL plus Selective Immersion Gold",+ "Lead-free HASL plus Selective Gold Plating"+ ],+ "maxBoardSize": {+ "xMm": 630,+ "yMm": 520+ },+ "notes": "Multi-layer board via/pad: 0.15mm inner diameter, 0.25mm outer diameter. Other limits as 2 layer entry.",+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "process": "advanced",+ "layerCount": 6,+ "minTraceWidth": {+ "mm": 0.076,+ "mil": 3.0,+ "condition": "1oz copper"+ },+ "minSpacing": {+ "mm": 0.076,+ "mil": 3.0,+ "condition": "1oz copper"+ },+ "minDrill": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minVia": {+ "drillMm": 0.15,+ "drillMil": 5.91,+ "padMm": 0.25,+ "padMil": 9.84+ },+ "annularRing": {+ "viaMm": 0.18,+ "viaMil": 7.09+ },+ "copperToBoardEdge": {+ "mm": 0.3,+ "mil": 11.81+ },+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": {+ "mm": 0.075,+ "mil": 2.95+ },+ "silkLineWidth": {+ "mm": 0.1,+ "mil": 3.94+ },+ "silkToCopper": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minCopperClearance": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pad edge to trace edge; BGA pad to trace 0.075mm (2.9528mil)"+ },+ "boardThicknessOptionsMm": [+ 0.6,+ 4.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2,+ 3,+ 4,+ 5,+ 6+ ],+ "surfaceFinishes": [+ "Bare Copper",+ "OSP",+ "HASL With Lead",+ "HASL Lead-free",+ "Immersion Gold",+ "Immersion Tin",+ "Immersion Silver",+ "Nickel Palladium Gold",+ "OSP plus Selective Immersion Gold",+ "Lead-free HASL plus Selective Immersion Gold",+ "Lead-free HASL plus Selective Gold Plating"+ ],+ "maxBoardSize": {+ "xMm": 630,+ "yMm": 520+ },+ "notes": "6 layer board thickness range 0.6 to 4.0mm, differs from 2 and 4 layer range 0.4 to 4.0mm. Other limits as 4 layer entry.",+ "sources": [+ {+ "url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",+ "dateRead": "2026-09-03"+ }+ ]+ }+ ]+}
rules/records/elecrow.jsonadded+208@@ -0,0 +1,208 @@+{+ "vendor": "Elecrow",+ "vendorSlug": "elecrow",+ "vendorUrl": null,+ "records": [+ {+ "process": "standard",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "minimum, recommend greater than 8 mil"+ },+ "minSpacing": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)"+ },+ "minDrill": {+ "mm": 0.3,+ "mil": 11.81+ },+ "minVia": {+ "drillMm": 0.3,+ "drillMil": 11.81,+ "padMm": null,+ "padMil": null+ },+ "annularRing": null,+ "copperToBoardEdge": null,+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": null,+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 5.91+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 0.6,+ 0.8,+ 1.0,+ 1.2,+ 1.6,+ 2.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2+ ],+ "surfaceFinishes": [+ "HASL",+ "HASL Lead Free",+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 550.0,+ "yMm": 550.0+ },+ "notes": "Specs apply to regular custom PCB online ordering service, 1 to 8 layers share these limits. Maximum size 55cm x 55cm, minimum board dimension 10mm. Inner layer copper 17um (0.5 oz) or 35um (1 oz). Order form also offers OSP finish, 2.5mm thickness, and min castellated hole 0.60mm. Drill tolerance plated 0.1mm, non-plated 0.05mm. Outline tolerance plus or minus 0.20mm. Min silkscreen text height 0.8mm.",+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "process": "standard",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "minimum, recommend greater than 8 mil"+ },+ "minSpacing": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)"+ },+ "minDrill": {+ "mm": 0.3,+ "mil": 11.81+ },+ "minVia": {+ "drillMm": 0.3,+ "drillMil": 11.81,+ "padMm": null,+ "padMil": null+ },+ "annularRing": null,+ "copperToBoardEdge": null,+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": null,+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 5.91+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 0.6,+ 0.8,+ 1.0,+ 1.2,+ 1.6,+ 2.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2+ ],+ "surfaceFinishes": [+ "HASL",+ "HASL Lead Free",+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 550.0,+ "yMm": 550.0+ },+ "notes": "Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. 4 layer adds two inner layers (G1, G2 gerbers). Inner layer copper 17um (0.5 oz) or 35um (1 oz).",+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "process": "standard",+ "layerCount": 6,+ "minTraceWidth": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "minimum, recommend greater than 8 mil"+ },+ "minSpacing": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)"+ },+ "minDrill": {+ "mm": 0.3,+ "mil": 11.81+ },+ "minVia": {+ "drillMm": 0.3,+ "drillMil": 11.81,+ "padMm": null,+ "padMil": null+ },+ "annularRing": null,+ "copperToBoardEdge": null,+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": null,+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 5.91+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 0.6,+ 0.8,+ 1.0,+ 1.2,+ 1.6,+ 2.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2+ ],+ "surfaceFinishes": [+ "HASL",+ "HASL Lead Free",+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 550.0,+ "yMm": 550.0+ },+ "notes": "Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. Inner layer copper 17um (0.5 oz) or 35um (1 oz).",+ "sources": [+ {+ "url": "https://www.elecrow.com/pcb-manufacturing.html",+ "dateRead": "2026-09-03"+ }+ ]+ }+ ]+}
rules/records/eurocircuits.jsonadded+502@@ -0,0 +1,502 @@+{+ "vendor": "Eurocircuits",+ "vendorSlug": "eurocircuits",+ "vendorUrl": null,+ "records": [+ {+ "process": "proto",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "all services, pattern class 6"+ },+ "minSpacing": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "track to track, pattern class 6; class 5 is 0.175 mm (6.8898 mil), class 7 is 0.125 mm (4.9213 mil)"+ },+ "minDrill": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "min finished PTH hole; NPTH 0.35 mm (13.7795 mil)"+ },+ "minVia": {+ "drillMm": 0.25,+ "drillMil": 9.84,+ "padMm": 0.6,+ "padMil": 23.62+ },+ "annularRing": {+ "viaMm": 0.125,+ "viaMil": 4.92,+ "note": "outer and inner, plated holes, pattern class 6; recommended NPTH annular ring 0.30 mm (11.811 mil)"+ },+ "copperToBoardEdge": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "outer layers, routed; inner layers 0.40 mm (15.748 mil)"+ },+ "holeToHole": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "drill to drill, edge to edge of TOOLSIZE"+ },+ "maskExpansion": {+ "mm": 0.03,+ "mil": 1.18,+ "condition": "mask annular ring MAR, LDI colors green, black, red, blue; PI white or transparent 0.10 mm (3.937 mil); minimum SM opening 0.40 mm (15.748 mil)"+ },+ "maskSliver": {+ "mm": 0.075,+ "mil": 2.95,+ "condition": "mask segment MSM, LDI colors; PI white or transparent 0.130 mm (5.1181 mil)"+ },+ "silkLineWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "min legend line width; min text height 1.00 mm (39.5 mil)"+ },+ "silkToCopper": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "legend to exposed copper or surface finished copper; also 0.10 mm to holes and cutouts"+ },+ "minCopperClearance": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "different nets, pattern class 6 (standard); IPI clearance unconnected hole to copper 0.200 mm (7.874 mil)"+ },+ "boardThicknessOptionsMm": [+ 1.55+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 1+ ],+ "surfaceFinishes": [+ "ENIG",+ "LF HAL"+ ],+ "maxBoardSize": {+ "xMm": 580.0,+ "yMm": 425.0+ },+ "notes": "Min board 20 x 20 mm. Base copper foil: outer layers 18 \u00b5m (0.5 oz), inner layers 35 \u00b5m (1 oz). Minimum pad diameter: PTH is finished hole plus 0.350 mm on outer and inner layers, NPTH is finished hole plus 0.250 mm. Tool size equals finished PTH hole size plus 0.10 mm (4 mil), NPTH tool size equals finished size. Drill bits in 0.05 mm increments. Standard PTH hole tolerance plus/minus 0.10 mm (0.20 mm range) for holes 4 mm or less, NPTH plus/minus 0.05 mm. Holes with finished size 0.45 mm or smaller are defined as via holes. Pattern class 5 (all services): track/gap 0.175 mm (6.8898 mil), OAR/IAR 0.150 mm (5.9055 mil), IPI 0.225 mm (8.8583 mil). Legend to board edge: 0.250 mm routing, 0.450 mm scoring. Soldermask design rules LDI: pad to pad 0.135 mm (5.315 mil), track to pad 0.090 mm (3.5433 mil); PI colors: pad to pad 0.330 mm (12.9921 mil), track to pad 0.190 mm (7.4803 mil). Mask overlap clearance MOC: LDI 0.060 mm (2.3622 mil), PI 0.090 mm (3.5433 mil).",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/pcb-proto/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/drilled-holes/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/soldermask/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/legend-print/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/copper-layers/",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "PCB proto"+ },+ {+ "process": "proto",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "outer and inner layers, pattern class 6"+ },+ "minSpacing": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "pattern class 6; class 5 is 0.175 mm (6.8898 mil)"+ },+ "minDrill": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "min finished PTH hole; NPTH 0.35 mm (13.7795 mil)"+ },+ "minVia": {+ "drillMm": 0.25,+ "drillMil": 9.84,+ "padMm": 0.6,+ "padMil": 23.62+ },+ "annularRing": {+ "viaMm": 0.125,+ "viaMil": 4.92,+ "note": "outer and inner, plated holes, pattern class 6; recommended NPTH 0.30 mm (11.811 mil)"+ },+ "copperToBoardEdge": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "outer layers, routed; inner layers 0.40 mm (15.748 mil)"+ },+ "holeToHole": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "drill to drill, edge to edge of TOOLSIZE"+ },+ "maskExpansion": {+ "mm": 0.03,+ "mil": 1.18,+ "condition": "MAR, LDI colors; PI white or transparent 0.10 mm (3.937 mil); min SM opening 0.40 mm (15.748 mil)"+ },+ "maskSliver": {+ "mm": 0.075,+ "mil": 2.95,+ "condition": "MSM, LDI colors; PI white or transparent 0.130 mm (5.1181 mil)"+ },+ "silkLineWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "min legend line width; min text height 1.00 mm (39.5 mil)"+ },+ "silkToCopper": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "legend to exposed copper"+ },+ "minCopperClearance": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "different nets, pattern class 6; IPI 0.200 mm (7.874 mil)"+ },+ "boardThicknessOptionsMm": [+ 1.55+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 1+ ],+ "surfaceFinishes": [+ "ENIG",+ "LF HAL"+ ],+ "maxBoardSize": {+ "xMm": 500.0,+ "yMm": 425.0+ },+ "notes": "4 layer max board size 500 x 425 mm. Same build parameters as 2 layer. Blind and buried vias not available in PCB proto.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/pcb-proto/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "PCB proto"+ },+ {+ "process": "standard",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pooling; non-pooling 0.090 mm (3.5433 mil)"+ },+ "minSpacing": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pooling; non-pooling 0.090 mm (3.5433 mil); pattern class table: class 6 track/gap 0.150 mm (5.9055 mil), class 7 0.125 mm (4.9213 mil), class 8 0.100 mm (3.937 mil), class 9 0.090 mm (3.5433 mil), class 5 0.175 mm (6.8898 mil)"+ },+ "minDrill": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "min finished PTH hole; NPTH 0.20 mm (7.874 mil); classification drill classes by service: class A (all services) PTH 0.50 mm (19.685 mil), class B PTH 0.35 mm (13.7795 mil), class C PTH 0.25 mm (9.8425 mil), class D PTH 0.15 mm (5.9055 mil), class E PTH 0.10 mm (3.937 mil)"+ },+ "minVia": {+ "drillMm": 0.1,+ "drillMil": 3.94,+ "padMm": 0.4,+ "padMil": 15.75+ },+ "annularRing": {+ "viaMm": 0.125,+ "viaMil": 4.92,+ "note": "outer and inner, plated holes, pattern class 6; class 8 is 0.100 mm (3.937 mil); recommended NPTH 0.30 mm (11.811 mil)"+ },+ "copperToBoardEdge": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "outer layers routed; inner layers routed 0.40 mm (15.748 mil); V-cut 0.45 mm (17.7165 mil) outer and inner"+ },+ "holeToHole": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "drill to drill, edge to edge of TOOLSIZE"+ },+ "maskExpansion": {+ "mm": 0.03,+ "mil": 1.18,+ "condition": "MAR, LDI colors; PI white or transparent 0.10 mm (3.937 mil); min SM opening 0.40 mm (15.748 mil)"+ },+ "maskSliver": {+ "mm": 0.075,+ "mil": 2.95,+ "condition": "MSM, LDI colors; PI white or transparent 0.130 mm (5.1181 mil)"+ },+ "silkLineWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "min legend line width; min text height 1.00 mm (39.5 mil)"+ },+ "silkToCopper": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "legend to exposed copper"+ },+ "minCopperClearance": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "different nets, pattern class 6 (default); class 5 0.175 mm (6.8898 mil), class 7 0.125 mm (4.9213 mil), class 8 0.100 mm (3.937 mil), class 9 0.090 mm (3.5433 mil); IPI unconnected hole to copper 0.200 mm (7.874 mil)"+ },+ "boardThicknessOptionsMm": [+ 1.0,+ 1.55,+ 2.4+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 0.67,+ 1,+ 2+ ],+ "surfaceFinishes": [+ "ENIG",+ "LF HAL",+ "Immersion Silver"+ ],+ "maxBoardSize": {+ "xMm": 580.0,+ "yMm": 425.0+ },+ "notes": "Min board 5 x 5 mm. Base copper foil pooling 2 layer: 12 \u00b5m (0.33 oz), 18 \u00b5m (0.5 oz), 35 \u00b5m (1 oz), 70 \u00b5m (2 oz); inner layers 18 \u00b5m and 35 \u00b5m. Minimum pad diameter: outer PTH finished hole plus 0.300 mm, outer NPTH plus 0.200 mm, inner PTH plus 0.350 mm, inner NPTH plus 0.250 mm. Classification min pattern values also limited by base copper foil: 12 \u00b5m 0.090 mm (3.5 mil), 18 \u00b5m 0.100 mm (4 mil), 35 \u00b5m 0.125 mm (5 mil), 70 \u00b5m 0.200 mm (8 mil), 105 \u00b5m 0.250 mm (10 mil), for both outer and inner layers. Drill class minimum TOOLSIZE: class A 0.60 mm (23.622 mil), B 0.45 mm (17.7165 mil), C 0.35 mm (13.7795 mil), D 0.25 mm (9.8425 mil), E 0.20 mm (7.874 mil); max board thickness per drill class: A and B 3.20 mm, C 2.40 mm, D 2.00 mm, E 1.60 mm; aspect ratio 1:8. TOOLSIZE equals finished PTH size plus 0.10 mm (4 mil). Soldermask colors pooling: green, blue, black, white, red; non-pooling transparent. Legend white one or both sides, non-pooling black and white.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/standard-pool/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "STANDARD pool"+ },+ {+ "process": "standard",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pooling; non-pooling 0.090 mm (3.5433 mil); inner layer same classification values"+ },+ "minSpacing": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pooling; non-pooling 0.090 mm (3.5433 mil); pattern class 6 is 0.150 mm (5.9055 mil)"+ },+ "minDrill": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "min finished PTH hole; NPTH 0.20 mm (7.874 mil); drill classes A 0.50 mm to E 0.10 mm finished PTH"+ },+ "minVia": {+ "drillMm": 0.1,+ "drillMil": 3.94,+ "padMm": 0.4,+ "padMil": 15.75+ },+ "annularRing": {+ "viaMm": 0.125,+ "viaMil": 4.92,+ "note": "outer and inner, plated holes, pattern class 6; recommended NPTH 0.30 mm (11.811 mil)"+ },+ "copperToBoardEdge": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "outer layers routed; inner layers routed 0.40 mm (15.748 mil); V-cut 0.45 mm (17.7165 mil)"+ },+ "holeToHole": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "drill to drill, edge to edge of TOOLSIZE"+ },+ "maskExpansion": {+ "mm": 0.03,+ "mil": 1.18,+ "condition": "MAR, LDI colors; PI 0.10 mm (3.937 mil); min SM opening 0.40 mm (15.748 mil)"+ },+ "maskSliver": {+ "mm": 0.075,+ "mil": 2.95,+ "condition": "MSM, LDI colors; PI 0.130 mm (5.1181 mil)"+ },+ "silkLineWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "min legend line width; min text height 1.00 mm (39.5 mil)"+ },+ "silkToCopper": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "legend to exposed copper"+ },+ "minCopperClearance": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "different nets, pattern class 6; IPI 0.200 mm (7.874 mil)"+ },+ "boardThicknessOptionsMm": [+ 1.0,+ 1.55+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 0.67,+ 1,+ 2+ ],+ "surfaceFinishes": [+ "ENIG",+ "LF HAL",+ "Immersion Silver"+ ],+ "maxBoardSize": {+ "xMm": 500.0,+ "yMm": 425.0+ },+ "notes": "4 layer pooling board thickness 1.00 mm; 1.55 mm pooling for 6 to 16 layers. Multilayer max dimension 500 x 425 mm. Standard buildups pooled, 8 predefined non-pooling builds; blind and buried vias non-pooling specials. Base copper inner layers pooling 18 \u00b5m and 35 \u00b5m.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/standard-pool/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "STANDARD pool"+ },+ {+ "process": "standard",+ "layerCount": 6,+ "minTraceWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pooling; non-pooling 0.090 mm (3.5433 mil)"+ },+ "minSpacing": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "pooling; non-pooling 0.090 mm (3.5433 mil)"+ },+ "minDrill": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "min finished PTH hole; NPTH 0.20 mm (7.874 mil)"+ },+ "minVia": {+ "drillMm": 0.1,+ "drillMil": 3.94,+ "padMm": 0.4,+ "padMil": 15.75+ },+ "annularRing": {+ "viaMm": 0.125,+ "viaMil": 4.92,+ "note": "outer and inner, plated holes, pattern class 6"+ },+ "copperToBoardEdge": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "outer layers routed; inner 0.40 mm (15.748 mil); V-cut 0.45 mm (17.7165 mil)"+ },+ "holeToHole": {+ "mm": 0.25,+ "mil": 9.84,+ "condition": "drill to drill, edge to edge of TOOLSIZE"+ },+ "maskExpansion": {+ "mm": 0.03,+ "mil": 1.18,+ "condition": "MAR, LDI colors; PI 0.10 mm (3.937 mil)"+ },+ "maskSliver": {+ "mm": 0.075,+ "mil": 2.95,+ "condition": "MSM, LDI colors; PI 0.130 mm (5.1181 mil)"+ },+ "silkLineWidth": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "min legend line width"+ },+ "silkToCopper": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "legend to exposed copper"+ },+ "minCopperClearance": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "different nets, pattern class 6; IPI 0.200 mm (7.874 mil)"+ },+ "boardThicknessOptionsMm": [+ 1.55+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 0.67,+ 1,+ 2+ ],+ "surfaceFinishes": [+ "ENIG",+ "LF HAL",+ "Immersion Silver"+ ],+ "maxBoardSize": {+ "xMm": 500.0,+ "yMm": 425.0+ },+ "notes": "6 and 8 layers pooling in STANDARD pool; 10 to 16 layers non-pooling. Pooling board thickness for multilayers 6 layers and above is 1.55 mm. Same pattern and drill classification system applies.",+ "sources": [+ {+ "url": "https://www.eurocircuits.com/services/standard-pool/",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "STANDARD pool"+ }+ ],+ "unreachable": [+ "https://www.eurocircuits.com/our-services/eurocircuits-pcb-specifications/ (404)"+ ]+}
rules/records/jlcpcb.jsonadded+290@@ -0,0 +1,290 @@+{+ "vendor": "JLCPCB",+ "vendorSlug": "jlcpcb",+ "vendorUrl": null,+ "records": [+ {+ "process": "standard",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.1,+ "mil": 4.0,+ "condition": "1 oz copper outer layer"+ },+ "minSpacing": {+ "mm": 0.1,+ "mil": 4.0,+ "condition": "1 oz copper, different nets"+ },+ "minDrill": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minVia": {+ "drillMm": 0.15,+ "drillMil": 5.91,+ "padMm": 0.25,+ "padMil": 9.84+ },+ "annularRing": {+ "viaMm": 0.18,+ "viaMil": 7.09,+ "note": "PTH, 1 oz outer, absolute minimum, recommended 0.25 mm"+ },+ "copperToBoardEdge": {+ "mm": 0.2,+ "mil": 7.87,+ "condition": "routed edge, 0.4 mm for V-cut edge"+ },+ "holeToHole": {+ "mm": 0.2,+ "mil": 7.87,+ "condition": "via hole to via hole, pad hole to pad hole is 0.45 mm"+ },+ "maskExpansion": {+ "mm": 0.0,+ "mil": 0.0,+ "condition": "LDI, 1:1 pad to soldermask opening since June 2025"+ },+ "maskSliver": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "1 oz, soldermask bridge, green/red/yellow/blue/purple, 0.13 mm for black/white, 0.20 mm for 2 oz"+ },+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 5.91+ },+ "silkToCopper": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "pad to silkscreen minimum distance"+ },+ "minCopperClearance": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "different nets, 1 oz"+ },+ "boardThicknessOptionsMm": [+ 0.4,+ 0.6,+ 0.8,+ 1.0,+ 1.2,+ 1.6,+ 2.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2,+ 2.5,+ 3.5,+ 4.5+ ],+ "surfaceFinishes": [+ "HASL leaded",+ "HASL lead-free",+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 670.0,+ "yMm": 600.0,+ "condition": "absolute max 1020 x 600 mm for 2 layer FR4"+ },+ "notes": "2 oz: min trace/spacing 0.16/0.16 mm (6.5/6.5 mil). 2.5 oz: 0.2/0.2 mm (8/8 mil). 3.5 oz: 0.25/0.25 mm (10/10 mil). 4.5 oz: 0.3/0.3 mm (12/12 mil). Min drill 0.15 mm costs more. Via diameter should be 0.1 mm (0.15 mm preferred) larger than via hole, preferred min via hole 0.2 mm. PTH annular ring 2 oz: 0.254 mm or above. NPTH pad annular ring 0.45 mm recommended. Min NPTH 0.5 mm. Min plated slot width 0.5 mm. Pad to track clearance 0.1 mm. SMD pad to pad clearance different nets 0.15 mm. Via hole to track 0.2 mm, PTH to track 0.28 mm (0.35 recommended), NPTH to track 0.2 mm. Same-net track spacing 0.25 mm. Min silk text height 1.0 mm (40 mil). Soldermask opening to neighboring trace clearance 0.09 mm. Trace width tolerance plus/minus 20 percent.",+ "sources": [+ {+ "url": "https://jlcpcb.com/capabilities/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "process": "standard",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.09,+ "mil": 3.5,+ "condition": "1 oz copper outer layer, 3 mil acceptable in BGA fan-outs"+ },+ "minSpacing": {+ "mm": 0.09,+ "mil": 3.5,+ "condition": "1 oz copper, different nets"+ },+ "minDrill": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minVia": {+ "drillMm": 0.15,+ "drillMil": 5.91,+ "padMm": 0.25,+ "padMil": 9.84+ },+ "annularRing": {+ "viaMm": 0.15,+ "viaMil": 5.91,+ "note": "PTH, 1 oz outer, absolute minimum, recommended 0.20 mm"+ },+ "copperToBoardEdge": {+ "mm": 0.2,+ "mil": 7.87,+ "condition": "routed edge, 0.4 mm for V-cut edge"+ },+ "holeToHole": {+ "mm": 0.2,+ "mil": 7.87,+ "condition": "via hole to via hole, pad hole to pad hole is 0.45 mm"+ },+ "maskExpansion": {+ "mm": 0.0,+ "mil": 0.0,+ "condition": "LDI, 1:1 pad to soldermask opening since June 2025"+ },+ "maskSliver": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "1 oz, soldermask bridge, green/red/yellow/blue/purple, 0.13 mm for black/white, 0.20 mm for 2 oz"+ },+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 5.91+ },+ "silkToCopper": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "pad to silkscreen minimum distance"+ },+ "minCopperClearance": {+ "mm": 0.09,+ "mil": 3.5,+ "condition": "different nets, 1 oz, 0.09 mm locally for BGA pads"+ },+ "boardThicknessOptionsMm": [+ 0.4,+ 0.6,+ 0.8,+ 1.0,+ 1.2,+ 1.6,+ 2.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2+ ],+ "surfaceFinishes": [+ "HASL leaded",+ "HASL lead-free",+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 663.0,+ "yMm": 593.0,+ "condition": "absolute max 1016 x 596 mm for 4 layer FR4"+ },+ "notes": "Same source page as 2 layer, multilayer column. Inner layer copper 0.5/1/2 oz, 0.5 oz default. Inner layer via hole to copper clearance 0.2 mm, inner PTH pad hole to copper clearance 0.3 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Min plated slot width 0.35 mm multilayer. Controlled impedance available. Blind/buried vias not supported, through holes only.",+ "sources": [+ {+ "url": "https://jlcpcb.com/capabilities/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+ },+ {+ "process": "standard",+ "layerCount": 6,+ "minTraceWidth": {+ "mm": 0.09,+ "mil": 3.5,+ "condition": "1 oz copper outer layer, 3 mil acceptable in BGA fan-outs"+ },+ "minSpacing": {+ "mm": 0.09,+ "mil": 3.5,+ "condition": "1 oz copper, different nets"+ },+ "minDrill": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minVia": {+ "drillMm": 0.15,+ "drillMil": 5.91,+ "padMm": 0.25,+ "padMil": 9.84+ },+ "annularRing": {+ "viaMm": 0.15,+ "viaMil": 5.91,+ "note": "PTH, 1 oz outer, absolute minimum, recommended 0.20 mm"+ },+ "copperToBoardEdge": {+ "mm": 0.2,+ "mil": 7.87,+ "condition": "routed edge, 0.4 mm for V-cut edge"+ },+ "holeToHole": {+ "mm": 0.2,+ "mil": 7.87,+ "condition": "via hole to via hole, pad hole to pad hole is 0.45 mm"+ },+ "maskExpansion": {+ "mm": 0.0,+ "mil": 0.0,+ "condition": "LDI, 1:1 pad to soldermask opening since June 2025"+ },+ "maskSliver": {+ "mm": 0.1,+ "mil": 3.94,+ "condition": "1 oz, soldermask bridge, green/red/yellow/blue/purple, 0.13 mm for black/white, 0.20 mm for 2 oz"+ },+ "silkLineWidth": {+ "mm": 0.15,+ "mil": 5.91+ },+ "silkToCopper": {+ "mm": 0.15,+ "mil": 5.91,+ "condition": "pad to silkscreen minimum distance"+ },+ "minCopperClearance": {+ "mm": 0.09,+ "mil": 3.5,+ "condition": "different nets, 1 oz"+ },+ "boardThicknessOptionsMm": [+ 0.4,+ 0.6,+ 0.8,+ 1.0,+ 1.2,+ 1.6,+ 2.0+ ],+ "copperWeightOptionsOz": [+ 1,+ 2+ ],+ "surfaceFinishes": [+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 656.0,+ "yMm": 586.0,+ "condition": "6 layer and above"+ },+ "notes": "Same source page as 2 layer, multilayer column. 6 layer and above boards only have ENIG surface finish. Via-in-pad epoxy filled and capped is the default process for 6 layer and above boards, compatible with via diameters 0.15 to 0.55 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Backdrill supported on 4 to 32 layer FR4, thickness 0.8 mm or more.",+ "sources": [+ {+ "url": "https://jlcpcb.com/capabilities/pcb-capabilities",+ "dateRead": "2026-09-03"+ }+ ]+ }+ ],+ "unreachable": [+ "https://jlcpcb.com/help/article/59-How-to-Set-Up-DRC-in-EAGLE (JS-rendered help article, no DRC numbers retrievable)"+ ]+}
rules/records/macrofab.jsonadded+281@@ -0,0 +1,281 @@+{+ "vendor": "MacroFab",+ "vendorSlug": "macrofab",+ "vendorUrl": null,+ "records": [+ {+ "process": "extended",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "extended specs, not available on 2 oz copper"+ },+ "minSpacing": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "extended specs, not available on 2 oz copper"+ },+ "minDrill": {+ "mm": 0.1016,+ "mil": 4.0+ },+ "minVia": {+ "drillMm": 0.1016,+ "drillMil": 4.0,+ "padMm": 0.254,+ "padMil": 10.0+ },+ "annularRing": {+ "viaMm": 0.0762,+ "viaMil": 3.0+ },+ "copperToBoardEdge": {+ "mm": 0.0762,+ "mil": 3.0+ },+ "holeToHole": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "NPTH drill to drill; PTH drill to drill 0.5 mm (19.69 mil)"+ },+ "maskExpansion": null,+ "maskSliver": {+ "mm": 0.1,+ "mil": 3.93,+ "condition": "soldermask dam minimum"+ },+ "silkLineWidth": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "silkscreen size minimum; text height minimum 0.8 mm (32 mil)"+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 1.6+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 1+ ],+ "surfaceFinishes": [+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 378.46,+ "yMm": 378.46+ },+ "notes": "Extended DRC minimums as published. Board thickness 1.6 mm standard, other custom thicknesses supported; thickness tolerance T below 1.0 mm plus minus 15 percent, 1.0 to 1.6 mm plus minus 10 percent, T at or above 1.6 mm plus minus 10 percent. Min via pad derived from published min drill plus 2x annular ring: 4 mil plus 6 mil. NPTH hole size tolerance plus minus 0.05 mm, PTH plus minus 0.08 mm. Board edge tolerance plus minus 0.15 mm. Extended option disabled for 2 oz copper. Paste aperture min 0.1524 mm, paste clearance 0.1524 mm. Silkscreen text height min 0.8 mm.",+ "sources": [+ {+ "url": "https://www.macrofab.com/capabilities/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.macrofab.com/pcba/specs/",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "extended manufacturing specifications"+ },+ {+ "process": "extended",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "extended specs, not available on 2 oz copper"+ },+ "minSpacing": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "extended specs, not available on 2 oz copper"+ },+ "minDrill": {+ "mm": 0.1016,+ "mil": 4.0+ },+ "minVia": {+ "drillMm": 0.1016,+ "drillMil": 4.0,+ "padMm": 0.254,+ "padMil": 10.0+ },+ "annularRing": {+ "viaMm": 0.0762,+ "viaMil": 3.0+ },+ "copperToBoardEdge": {+ "mm": 0.0762,+ "mil": 3.0+ },+ "holeToHole": {+ "mm": 0.1524,+ "mil": 6.0,+ "condition": "NPTH drill to drill; PTH drill to drill 0.5 mm (19.69 mil)"+ },+ "maskExpansion": null,+ "maskSliver": {+ "mm": 0.1,+ "mil": 3.93,+ "condition": "soldermask dam minimum"+ },+ "silkLineWidth": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "silkscreen size minimum; text height minimum 0.8 mm (32 mil)"+ },+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 1.6+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 1+ ],+ "surfaceFinishes": [+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 378.46,+ "yMm": 378.46+ },+ "notes": "Same extended DRC table published for all layer counts; MacroFab supports 2 to 36 layer boards per capabilities page. 2 oz copper requires larger trace, spacing, annular ring and disables the extended option; specific 2 oz numbers not published on the read pages.",+ "sources": [+ {+ "url": "https://www.macrofab.com/capabilities/",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://www.macrofab.com/pcba/specs/",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "extended manufacturing specifications"+ },+ {+ "process": "standard",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "standard manufacturing specifications"+ },+ "minSpacing": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "standard manufacturing specifications"+ },+ "minDrill": {+ "mm": 0.3048,+ "mil": 12.0+ },+ "minVia": null,+ "annularRing": null,+ "copperToBoardEdge": null,+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": null,+ "silkLineWidth": null,+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 1.6+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 1+ ],+ "surfaceFinishes": [+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 378.46,+ "yMm": 378.46+ },+ "notes": "Standard (default, non-extended) manufacturing specifications per MacroFab help article: minimum trace width 5 mil, minimum drill 12 mil; page notes the standard tier was later reduced (5 mil spacing, 10 mil drill announced December 2018) but the help article body was only visible via search index, not fully readable on load.",+ "sources": [+ {+ "url": "https://support.macrofab.com/s/article/pcb-specifications-and-drc",+ "dateRead": "2026-09-03"+ },+ {+ "url": "https://support.macrofab.com/s/article/can-i-customize-my-pcb",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "standard manufacturing specifications"+ },+ {+ "process": "standard",+ "layerCount": 4,+ "minTraceWidth": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "standard manufacturing specifications"+ },+ "minSpacing": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "standard manufacturing specifications"+ },+ "minDrill": {+ "mm": 0.3048,+ "mil": 12.0+ },+ "minVia": null,+ "annularRing": null,+ "copperToBoardEdge": null,+ "holeToHole": null,+ "maskExpansion": null,+ "maskSliver": null,+ "silkLineWidth": null,+ "silkToCopper": null,+ "minCopperClearance": {+ "mm": 0.127,+ "mil": 5.0,+ "condition": "different nets"+ },+ "boardThicknessOptionsMm": [+ 1.6+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 1+ ],+ "surfaceFinishes": [+ "ENIG"+ ],+ "maxBoardSize": {+ "xMm": 378.46,+ "yMm": 378.46+ },+ "notes": "Same standard specifications as 2-layer; help article does not differentiate by layer count.",+ "sources": [+ {+ "url": "https://support.macrofab.com/s/article/pcb-specifications-and-drc",+ "dateRead": "2026-09-03"+ }+ ],+ "processDetail": "standard manufacturing specifications"+ }+ ],+ "unreachable": [+ "https://help.macrofab.com/docs/design-rules/standard-pcb-design-rules (JS shell only, no content rendered)",+ "https://support.macrofab.com/s/article/pcb-specifications-and-drc (JS shell only, content visible in search index)"+ ]+}
rules/records/nextpcb.jsonadded+77@@ -0,0 +1,319 @@+{+ "vendor": "NextPCB",+ "vendorSlug": "nextpcb",+ "vendorUrl": null,+ "records": [+ {+ "process": "standard",+ "layerCount": 2,+ "minTraceWidth": {+ "mm": 0.0635,+ "mil": 2.5,+ "condition": "H/HOZ 0.5oz inner layer copper"+ },+ "minSpacing": {+ "mm": 0.0762,+ "mil": 3.0,+ "condition": "H/HOZ 0.5oz inner layer copper"+ },+ "minDrill": {+ "mm": 0.15,+ "mil": 5.91+ },+ "minVia": {+ "drillMm": 0.2,+ "drillMil": 7.87,+ "padMm": 0.3278,+ "padMil": 12.91+ },+ "annularRing": {+ "viaMm": 0.0889,+ "viaMil": 3.5+ },+ "copperToBoardEdge": {+ "mm": 0.2,+ "mil": 7.87+ },+ "holeToHole": {+ "mm": 0.3048,+ "mil": 12.0+ },+ "maskExpansion": {+ "mm": 0.0381,+ "mil": 1.5+ },+ "maskSliver": {+ "mm": 0.0889,+ "mil": 3.5+ },+ "silkLineWidth": {+ "mm": 0.0762,+ "mil": 3.0+ },+ "silkToCopper": {+ "mm": 0.1524,+ "mil": 6.0+ },+ "minCopperClearance": {+ "mm": 0.1778,+ "mil": 7.0,+ "condition": "via to track"+ },+ "boardThicknessOptionsMm": [+ 0.6,+ 0.8,+ 1.0,+ 1.2,+ 1.6,+ 2.0,+ 2.5,+ 3.0,+ 3.2+ ],+ "copperWeightOptionsOz": [+ 0.5,+ 1,+ 2+ ],