PCB Design Rules

@@ -0,0 +1,3 @@+# PCB Design Rules++Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

@@ -0,0 +1,32 @@+{+  "schema_version": 1,+  "slug": "pcb-design-rules",+  "type": "skill",+  "title": "PCB Design Rules",+  "brief": "Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.",+  "version": "0.1.0",+  "hero": {+    "type": "billboard",+    "headline": "Design rules for every fab, one page",+    "subhead": "JSON records plus ready-to-load Fusion, KiCad and Altium rule files for 14 PCB vendors"+  },+  "author": {+    "name": "John Lauer",+    "email": "[email protected]"+  },+  "tags": [],+  "license": "proprietary",+  "visibility": {+    "public": true+  },+  "sample_prompts": [],+  "discovery_triggers": [],+  "discovery_pitch": null,+  "metadata": {},+  "created_at": "2026-09-03T12:39:44.118Z",+  "updated_at": "2026-09-03T12:39:44.118Z",+  "source_path": "SKILL.md",+  "sub_skills": [],+  "parent_app": null,+  "org": "adom"+}\ No newline at end of file