AFS_Adom flight computer molecule

An active fin stabilization (AFS) flight computer for a sounding rocket: an RP2350B reading four motion and pressure sensors and driving eight fin servos from a 2S LiPo, on a 4-layer 92 x 68 mm board. Every step was done by an AI through KiCad: the architecture, the 7-sheet schematic, the layout, the analyses, the silkscreen and the factory files. It started from one written brief.

The finished board in KiCad's 3D viewer. Yellow block: the XT30 battery connector (placeholder body). Eight servo headers run along the top edge.

Why this project is interesting

This board is a clean-room copy of a real one: the flight computer used by the Rice Eclipse active fin stabilization subteam. Students on the subteam designed their version by hand in KiCad. This version was given the same job (the same sensors, servo count, battery, connectors and fab) and was designed end to end by an AI, Claude, driving KiCad through the Adom Bridge. The AI never saw the student design.

That makes it a fair side-by-side. One board is the work of strong college KiCad designers. The other shows where AI-driven PCB tools are today. Comparing the two answers practical questions: where the tool is already as good as a careful student, where it is better, and where a human is still clearly ahead.

What the AI did on its own, from one brief:

• Architecture with reasons. It picked an ideal-diode OR of USB and battery so the MCU never resets when a source is swapped, and sized the 5 mOhm current shunt for an 8 A all-servo stall. It also chose bucks over LDOs: at 8.4 V an LDO would burn 5 W.
• Footprints for parts with no library. It drew footprints from the datasheets for the ICM-45686, KX134, MMC5983MA, TMP117 and INA219.
• The hard part of the layout. It escaped a 0.4 mm-pitch QFN-80 under PCBWay rules with a pre-routed fan-out. The 415 traces were then landed live in KiCad, one undo step each, ending at 0 DRC errors and 0 unconnected.
• Physics, not just DRC. It solved current density and temperature on the real copper with Adom Fields and fixed what the solve found: necks in the 5 V and VSYS paths, a battery patch that blocked the ground return, missing stitching vias. It also ran ngspice simulations of the power path, the servo stall and both bucks.
• A paper trail. A 48-entry iteration log records every failed attempt, budget change and tool bug, so a reviewer can see why each decision was made.

Compared with the student board

Both boards were run through the same checks from their KiCad files. The full write-up, with drawings, is on the comparison page.

Same loads, same scale, simulated. The student board is about 30 % smaller and narrow enough for the airframe. Its bottom-side buck runs about 30 C hotter because it has no ground vias under it.

Where a human still wins, honestly:

• Judgment calls. Two budgets were loosened on the record: the thermal rise went from 30 to 35 C, and the steady-state servo current from 8 to 4 A sustained. Both have physical reasons, but they deserve a human's eye.
• Silkscreen density. At PCBWay's 0.8 mm minimum, labels for some small parts would not fit.
• The tool loop. Fixing the current-density screen took about a dozen land-solve-fix loops.
• Nothing is proven until it is built. No board has been made yet.

Gallery

Top face. Power on the left (XT30, TVS, shunt, the two bucks and their inductors), RP2350B in the middle, the sensor cluster to the right away from the inductors, microSD lower right, USB-C bottom centre.

Bottom face. This side is the service manual: every through-hole header and molecule contact is named, plus a key from test point to net and what the board is.

The RP2350B (QFN-80, 0.4 mm pitch) with its decoupling ring, the 12 MHz crystal and the core regulator inductor.

The routed board in KiCad's PCB editor: 4 layers, 2190 track segments, 508 vias.

Heat flow in the copper with each hot part's rise: both bucks about +27 C, the shunt +25 C, the ideal-diode FET +23 C, the RP2350 +19 C, in still air.

Current density in all four layers, exploded. Every loaded net stays under the 60 A/mm2 screen; the worst is 59 A/mm2 on VSYS.

The full gallery has more views: the side profile, the VSYS and ground nets, the schematic, the temperature map, the current-density drawing and the three ngspice simulations. See docs/gallery.md.

How the AI built it (narrated)

The run's own cut, assembled by adom-aiflow from the clips recorded at every step, with captions. Every step clip, including the failed attempts, is on the clips page. The run's timeline is on the run page.

What is on the board

Files

Status: rev A, design complete, not yet fabricated. Every electrical and thermal figure here is a design limit or a simulation; nothing has been measured yet. One BOM line, the XT30PW-M, is LCSC-only; the owner accepted it.