# AFS_Adom board audit (adom/kicad-board-audit checklist), 2026-10-16

Board: AFS_Adom.kicad_pcb (KiCad 10.0.6, 92 x 68 mm, 4 layers), schematic AFS_Adom.kicad_sch + power / mcu / sensors / servos / connectors / molecule sheets. Checkers run on the user's desktop through the KiCad bridge (kicad-cli 10.0.6), the netlist compared pin by pin with the board (aiflow `netlist check --net`, 493/493 pins).

## 1. Real checkers

| Check | Result | Silenced rules (read before trusting) |
|---|---|---|
| ERC | 0 errors, 3 warnings (MS5611-01BA03 symbol pin types vs the shared SPI bus, explained in DESIGN_NOTES §2) | ERC `ignore`: footprint_filter, four_way_junction, simulation_model_issue, single_global_label (KiCad defaults) |
| DRC, live board | 0 errors, 0 warnings, 0 unconnected | DRC `ignore`: track_dangling, via_dangling (the pre-routed stubs on the RP2350's unused pins), isolated_copper (pour islands), copper_sliver, lib_footprint_issues / lib_footprint_mismatch (the AI-created footprints differ from the library originals they were derived from), plus KiCad's own defaults (missing_courtyard, courtyard hole checks, footprint_type/filters_mismatch, track_not_centered_on_via, tuning_profile_track_geometries). None of these hides a copper error: with every class at `warning` the board reported 0 errors / 130 warnings, all in those classes. |
| Unconnected items | 0 | none |
| Netlist vs board | 172 refs, 493/493 connected pins on the same net | none |

## 2. Checklist walk

| Item | Finding | Severity |
|---|---|---|
| Floating mandatory pins | RP2350B: DVDD (pins 10/32/51/65) fed by the on-chip VREG (VREG_LX through 3.3 uH to DVDD, VREG_AVDD filtered), all IOVDD pins on +3V3, QSPI pins to W25Q128, USB_VDD, ADC_AVDD on +3V3 per the datasheet power table; no unconnected supply pin. ICM-45686, KX134, MMC5983MA, MS5611, TMP117, INA219: every VDD/VDDIO pin on +3V3, every GND/EP on GND (netlist). | none |
| Supply pins tied to GND by mistake | none (every power pin's net checked in the netlist: +3V3 75 pads, GND 124 pads, no cross) | none |
| Strap / boot pins | QSPI_SS pulled up 10 k (R10), BOOTSEL button through 1 k (R11) to GND (RP2350 hardware design guide); RUN pulled up 10 k (R12) with the RESET button to GND; no other RP2350 boot strap. The four sensors' interface-select / address straps are tied for 4-wire SPI as the sensors sheet's notes state per datasheet; each has its own CS and interrupt GPIO. | none |
| Regulator feedback | AP63205 / AP63203 are fixed-output parts (FB is the VOUT sense pin, no divider): nothing to miscompute. LTC4359 gate drive straps per Rev C datasheet. | none |
| Pull-ups on open-drain buses | I2C0: 4.7 k to +3V3 on SDA/SCL (R17/R18); I2C1: 4.7 k (R27/R28); microSD CS/MOSI/MISO/DAT1/DAT2/CD 10 k (R21-R26); TMP117 ALERT open-drain with 10 k (R16). Sensor interrupt lines are push-pull outputs. | none |
| Crystal | 12 MHz ABM8-272-T3 (CL 10 pF) with 2 x 15 pF (C33/C34) and the RP2350's XOUT series resistor (R9 1 k): CL = C/2 + Cstray ~ 7.5 + 2.5 pF = 10 pF, as the datasheet example. Crystal 1.1 mm from the XIN/XOUT pins, hand-routed, GND pour kept out under it (planeUnder note in the spec). | none |
| Impedance / net classes | USB D+/D- routed as a loosely coupled pair with 27 R series resistors at the RP2350 (hardware guide); no controlled-impedance stack-up was requested and PCBWay standard 4-layer is not impedance-controlled: USB 2.0 full-speed is what the RP2350 bootloader uses, fine at this length (< 30 mm). Noted in DESIGN_NOTES §1.9. | low |
| Unrouted nets | 0 (gate and live DRC) | none |
| Keepouts | 13 Kelvin / plane keepouts from the pour plan (the shunt sense pair, no pour under the crystal and the switch nodes: spec.noPour) landed and verified by the pour preflight. | none |
| Current / thermal | Adom Fields on the final copper: every loaded net under 60 A/mm2 at the sustained loads; hot parts U5 27.4, U6 27.0, R1 24.8, Q1 22.6, U1 19.1 C rise still air against 35 C. Budgets amended on the record (DESIGN_NOTES §3.5). | low (review the two amendments) |
| Decoupling (Fields heuristics) | "decoupling-missing" on U5/U6 BST and SW pins (not supply pins) and on U13's SERVOx outputs (logic outputs); "decoupling-far" on U1/U6 +3V3 (IOVDD caps 4 mm from the pins because the fan-out band must stay clear: 12 x 100 nF around the package, within 4 mm). Reviewed, no change. | low |
| Signals over the +3V3 plane | ACC_CS (23 mm), ACC_INT1 (18 mm) and a few sensor lines run over In2 (+3V3) rather than In1 (GND) on B.Cu; their return rides +3V3 through the bypass caps. Slow signals (SPI 1-10 MHz, interrupts), acceptable. | low |
| Silkscreen | 294 labels, PCBWay 0.8 mm minimum; 65 top-face labels did not fit (listed in DESIGN_NOTES §3.6); the fab's own silk-over-pad clipping leaves nothing (0 warnings). | low |
| Placeholders | AI-created STEP boxes for RP2350B, KX134, XT30PW-M (3d/*.provenance.json); replace before mechanical integration. | low |
| Sourcing | J1 XT30PW-M has no Mouser/DigiKey listing (LCSC C431092 only); the run's fab-profile sourcing gate refuses it, the brief allows LCSC. User decision. | medium (process) |

## 3. Verdict

No fab blocker found in the copper or the netlist: 0 DRC errors, 0 unconnected, 0 ERC errors, netlist equals the board, every current and thermal gate passed on the final copper. The open items are process ones: the J1 sourcing profile, the two amended budgets to acknowledge, the placeholder 3D bodies, and the silkscreen coverage the 0.8 mm rule leaves.