skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
Pull Requests
Disable the all/all same-signal 'Same-net track spacing' rule: it reports every trace joint as an Overlap warning
#1 Merged · opened by John Lauer 2026-09-07