PCB Design Rules

Scope: KiCad rule syntax only; no fabrication limits changed

The published generator emits (constraint hole (min ...)) in all 55 generated .kicad_dru files. Native KiCad 10 custom-rule parsing rejects every file with unknown constraint type 'hole'. The valid KiCad keyword is hole_size.

This draft makes exactly one source-code line change in tools/generate.py:

• hole → hole_size

It changes no canonical vendor record, no minimum clearance, no drill dimension and no policy, and includes no regenerated production rule files. Its merge cannot silently publish or substitute a new PCBWay manufacturing profile. It is intentionally narrow and can be cherry-picked into the existing broader adom/pcb-design-rules draft PR #2 (global ID 98), if maintainers prefer one PR.

Reproduction

• Before: 55/55 generated KiCad DRUs invalid at parser.
• Scratch regenerated with only the one-line change: 55 valid, 0 invalid, 0 parser errors using the native ADOM KiCad bridge parser (KiCad 10.0.7).
• Source rules/records/pcbway.json and every other canonical fab record unchanged.
• Independent scratch validation log retained in PCB Design Studio alongside upstream issue #6.

NOT a complete manufacturing fix

This repair only makes the published generator emit syntactically loadable files. It does not prove KiCad enforces the source's annular-width, hole-to-hole, layer/copper-weight, mask, silk, or clearance-precedence requirements. ADOM's existing draft PR #2, issues #2, #4, #5 and #6 cover larger generator and manufacturer-source gaps. Those must be resolved with native DRC negative-control coupons and full source reconciliation before regenerated production DRUs are published.

The related UMCU21 project remains at Stage 2 Rules HOLD, with Stage 3 locked; no PCBWay production release is authorised.

Draft / review requested — do not merge this into a rules release without considering overlap with existing PR #2.