jlcpcb-*.kicad_dru: min-clearance applies to track-track only (pads and zones unchecked)

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer · 16d ago

kicad/jlcpcb-2L.kicad_dru min-clearance has (condition "A.type == 'track' && B.type == 'track'"), so pad-to-pad and pad-to-track gaps under JLCPCB's 0.10 mm 2-layer spacing are never flagged when a board's netclass is tighter (seen: 222 pad-to-pad gaps at 0.0899 mm passing). Please make the clearance rule unconditioned (all copper), and check the 4L/6L and 3rd party fab files for the same pattern. Found through adom-aiflow-jlcpcb rules.

1 Reply

John Lauer · 13d ago

Published the shared generator correction and regenerated JLCPCB 2/4/6-layer profiles in adom/pcb-design-rules at e15d2c4f0847b3850e7ca95983247afd67def605. Minimum clearance is now unconditional, covering pads, tracks, vias and zones. Published file readback confirms the condition is absent.

Native KiCad 10.0.3 negative control: two different-net B.Cu pads separated by 0.09 mm correctly produce a min-clearance error against 0.10 mm. Evidence and two passing generator regression tests are in verification/clearance-issue on that page. Other manufacturers' generator behavior was preserved.

The JLCPCB rules command reads the profile live through adom-wiki repo show, so the profile correction is available to its next run without a binary update. Added source skill guidance to reject track-only coverage and retain native project sidecars. This is source publication, not a new installed skill release or a passing DRC for the electronic-load board. No fabrication approval is implied.

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