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PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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PCBWay 4L 1oz: conservative sourced minima; hold until KiCad generator qualified #5

Open Draft opened by Josh Aberdeen 2026-11-01
Mentions #2 Mentions #4

PCBWay standard 4-layer 1 oz record — conservative source reconciliation (DRAFT ONLY)

This proposal changes only the standard 4-layer record in rules/records/pcbway.json. All other records remain byte-for-byte equivalent at the JSON object level. It is not a relaxation and is not permission to merge or publish production DRUs.

Source-backed choices

  • Conventional 1 oz outer track width 5 mil = 0.127 mm and spacing 6 mil = 0.1524 mm; the single 4-layer record applies these stricter outer limits globally rather than the looser inner 4/5 mil. The record's condition explicitly limits the interpretation to 1 oz copper.
  • Via annular ring 0.15 mm, corroborated by PCBWay capabilities and manufacturing tolerances.
  • 1 oz outer plated component-hole annular ring 0.254 mm (10 mil) from the standard capabilities table. PCBWay's tolerances page describes a weaker 0.20 mm normal value; we explicitly retain the more conservative 0.254 mm and record the discrepancy.
  • Via pad diameter 0.50 mm derived from 0.20 mm drill + 2 x 0.15 mm annular ring, not represented as a separately published manufacturer minimum.
  • Hole-to-hole 0.45 mm globally, conservatively covering the newer PCBWay Help Center advice of 0.45 mm for different-net PTH holes and 0.30 mm for via holes. The standard capabilities table has older/lower 16/11 mil values; the disagreement is documented.
  • The existing 0.20 mm drill minimum is unchanged (more conservative than a 0.15 mm base threshold listed on the standard page).

Official PCBWay sources:

All sources were archived with SHA-256 in the private UMCU21 Stage 2 evidence; see PCB Design Studio PR #162.

Merge blockers / review requirements

  1. These values are only justified for 4-layer standard, 1 oz outer and inner. Copper weights and fabrication tiers require separately qualified limits; the generic record should not silently claim coverage.
  2. The existing ADOM generator does not yet emit the source's separate via/PTH annular-width or hole-spacing enforcement. Its hole constraint syntax also fails KiCad parsing. The source updates are not useful until the KiCad generator is safely corrected (upstream PR #2 and syntax-only draft PR #4).
  3. The final generated DRU still requires negative and positive native KiCad DRC tests for pad/via/PTH and copper zones, silkscreen and solder mask, plus confirmation it does not lower a board's stricter netclass/zone clearances (see upstream issue #5).
  4. UMCU21 cannot progress beyond ADOM Stage 2 Rules until an actual correct published profile is loaded via native ADOM rules commands and source hashes and all independent acceptance checks pass.

Submit for maintainer technical review only. Do not merge until those blockers are resolved. No live ADOM rule, user PCB, PostgreSQL gate or manufacturing order was altered.

Diff Skip to comments

--- a/rules/records/pcbway.json+++ b/rules/records/pcbway.json@@ -1,616 +1,644 @@⋯ 105 unchanged lines ⋯       "process": "standard",       "layerCount": 4,       "minTraceWidth": {-        "mm": 0.1016,-        "mil": 4.0,-        "condition": "inner layer, 1oz (35um) copper, before compensation; inner 0.5oz: 4mil, 2oz: 6mil, 3oz: 8mil. Outer layer 1oz: 5mil"-      },-      "minSpacing": {         "mm": 0.127,         "mil": 5.0,-        "condition": "inner layer, 1oz (35um) copper, before compensation; inner 0.5oz: 5mil (4/4mil class), 2oz: 8mil, 3oz: 11mil. Outer layer 1oz: 6mil"+        "condition": "4L 1oz: outer conventional 5mil (0.127) applied to every layer; inner 4mil (0.1016) is looser, not used. Sources: capabilities table (std sha 694ce30266e8); mobile page suggests 6mil. "       },+      "minSpacing": {+        "mm": 0.1524,+        "mil": 6.0,+        "condition": "4L 1oz: outer conventional 6mil (0.1524) applied to every layer; inner 5mil (0.127) looser, not used. Sources: capabilities table (std sha 694ce30266e8); mobile page suggests 6mil."+      },       "minDrill": {         "mm": 0.2,         "mil": 7.87⋯ 1 unchanged line ⋯       "minVia": {         "drillMm": 0.2,         "drillMil": 7.87,-        "padMm": 0.454,-        "padMil": 17.87+        "padMm": 0.5,+        "padMil": 19.69,+        "note": "derived: drill 0.2 + 2 x 0.15 via ring (vendor page does not publish a via pad)"       },       "annularRing": {-        "viaMm": 0.127,-        "viaMil": 5.0,-        "note": "via, 1oz outer copper; component hole 1oz: 10mil"+        "viaMm": 0.15,+        "viaMil": 6.0,+        "padMm": 0.254,+        "padMil": 10.0,+        "note": "viaMm: pads with vias, 0.15mm (6mil): capabilities page AND manufacturing-tolerances page (0.15 via ring) agree. padMm: 1oz outer component-hole ring 10mil (0.254) from the capabilities table; the manufacturing-tolerances page gives 0.20 for the PTH ring, which is WEAKER and not used. Source disagreement recorded in notes."       },       "copperToBoardEdge": {         "mm": 0.25,⋯ 1 unchanged line ⋯         "condition": "line to board edge, CNC routing"       },       "holeToHole": {-        "mm": 0.2794,-        "mil": 11.0,-        "condition": "via hole to via hole, via diameter 0.45mm or less; component holes: 16mil (0.4064mm)"+        "mm": 0.45,+        "mil": 17.72,+        "condition": "different-net plated holes: 0.45mm (limited_holes_spacing page, last updated 2025-06-25) - stricter than the capabilities table (16mil = 0.4064 PTH; 11mil = 0.2794 via). Via-to-via 0.30mm on that page is looser than 0.45 and is not used separately: 0.45 applies to all pairs (conservative)."       },       "maskExpansion": {         "mm": 0.0508,⋯ 49 unchanged lines ⋯         {           "url": "https://www.pcbway.com/capabilities.html",           "dateRead": "2026-09-03"+        },+        {+          "url": "https://www.pcbway.com/capabilities.html",+          "dateRead": "2026-11-02",+          "archiveSha256": "694ce30266e8c0bde8173d590c3ac71e6d928eb730fad3555e6a1dd298e0a980",+          "note": "observational archive; page footer '© 2024 PCBWay' only; no vendor revision date"+        },+        {+          "url": "https://www.pcbway.com/helpcenter/Engineering_Questions/limited_holes_spacing.html",+          "dateRead": "2026-11-02",+          "archiveSha256": "9cebdeed859c3c61d4e104185aa5e6a54fb1a5c6ac5864591fbd5993479145e1",+          "note": "official PCBWay Engineering Questions page; states last updated 2025-06-25"+        },+        {+          "url": "https://www.pcbway.com/pcb_prototype/PCB_Manufacturing_tolerances.html",+          "dateRead": "2026-11-02",+          "archiveSha256": "51142afe99832cc0ee41af19bf7d4c552a2658da466f04850523fab09bb66948",+          "note": "official PCBWay tolerances page; PTH ring 0.20 and via ring 0.15 (PTH ring weaker than capabilities table, not used)"+        },+        {+          "url": "https://m.pcbway.com/capabilities.html",+          "dateRead": "2026-11-02",+          "archiveSha256": "d7be6170136dad3df83304c5e34dab85775f7df80e632d8de8eae85969da3357",+          "note": "mobile capabilities page (summary only): drill 0.2 min, trace/spacing 4mil min with 6mil suggested, annular 0.15"         }       ]     },⋯ 414 unchanged lines ⋯     "https://www.pcbway.com/advanced-pcb.html"   ] }+

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