PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
KiCad generated DRUs 55/55 invalid; PCBWay 4L outer/PTH minima need source audit
Verified problem: all generated KiCad DRUs fail parser
Using the current publicly served adom/pcb-design-rules source and the native KiCad custom-rules parser through ADOM bridge, we tested all 55 generated kicad/*.kicad_dru files across 13 vendors. 55/55 were rejected, each with rule min-hole: unknown constraint type 'hole'; rule_count=0. In tools/generate.py the generator emits (constraint hole (min ...)), while KiCad expects hole_size. We reproduced the served pcbway-4L.kicad_dru byte-for-byte from the unmodified generator (SHA-256 09074b07419730ebac73432d37acc946d9c10706ac323d2651142c5eb65f7244).
An isolated candidate changed hole to hole_size and generated annular-width/hole-to-hole rules from already recorded fields. 55/55 then passed syntax parsing, but that is expressly not evidence that the rules enforce all actual fab capabilities; no production files were modified, no UMCU21 ADOM Rules gate accepted.
PCBWay 4-layer source-applicability audit: additional under-enforcement
For standard 4L with 1 oz outer and inner copper, PCBWay's capabilities table (https://www.pcbway.com/capabilities.html, read 2026-11-02) distinguishes:
- 35 µm inner-layer conventional track width/spacing >= 4/5 mil;
- 35 µm outer-layer conventional track width/spacing >= 5/6 mil;
- outer 35 µm annular ring: via-hole >= 5 mil, component-hole >= 10 mil, with an additional generic statement for pads with vias in the middle >= 0.15 mm;
- component-hole to component-hole >= 16 mil; via-to-via (<=0.45 mm) >= 11 mil;
- four-layer minimum inner hole-to-copper isolation >= 7 mil.
The existing generated PCBWay 4L pack carries a *.Cu 4/5 mil track/spacing pair, leaving outer-layer 1 oz clearances below the conventional values; it has no distinct PTH annular constraint or inner hole-isolation rule. The candidate's annular_width (min 0.15mm) applied indiscriminately to via and pad does not enforce conventional 0.254 mm component-hole annular ring. Because conditions are part of KiCad's precedence and applicability, a syntax-parse PASS alone cannot resolve these defects.
Requested maintainer path
- Fix the invalid
holegenerator keyword and add regression coverage for all generated KiCad DRUs. - Audit PCBWay 4L and other vendors' source applicability by copper weight, layer and drill-pad type; distinguish more conservative overall values from properly conditioned rules.
- Verify actual native DRC negative controls for track/via/PTH/zone/netclass clearance, annular width, hole-to-hole and hole-to-copper; validate Board Setup constraints separately.
- Cross-check existing upstream discussion PR #2 (global ID 98), issues #2, #4 and #5 before modifying shared generator behaviour. In particular, issue #5 documents that an unconditional minimum clearance can reduce a board's intended zone/netclass spacing.
- Publish regenerated rules only after engineering source/negative-control review; do not merge or bulk change 55 vendors on syntax success alone.
The isolated proposal and source-hash evidence are in PCB Design Studio draft PR #162: https://github.com/Unclefungussz/PCB-Design-Studio-/pull/162 (studio-control/manufacturing/postgres/upstream-adom-proposal/). The existing UMCU21 Stage 2 is HOLD on the native loaded pack; Stage 3 remains locked. No fabrication, firmware, CAD or live rule setting has been overridden.
The objective is a correct, reviewable upstream correction, not a workaround that marks a bad rule as passed.
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