skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
main
John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
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{
"vendor": "Seeed Fusion",
"vendorSlug": "seeed-fusion",
"vendorUrl": null,
"records": [
{
"process": "standard",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "1 oz copper, 4/4 mil option"
},
"minSpacing": {
"mm": 0.1016,
"mil": 4.0,
"condition": "1 oz copper, 4/4 mil option"
},
"minDrill": {
"mm": 0.2,
"mil": 7.87
},
"minVia": {
"drillMm": 0.2,
"drillMil": 7.87,
"padMm": 0.4,
"padMil": 15.75
},
"annularRing": {
"viaMm": 0.1,
"viaMil": 3.94,
"note": "vias, PTH is 0.152 mm (5.9843 mil)"
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 11.81
},
"holeToHole": {
"mm": 0.3,
"mil": 11.81,
"condition": "vias, PTH is 0.45 mm (17.7165 mil)"
},
"maskExpansion": {
"mm": 0.1,
"mil": 3.94,
"condition": "solder mask dam, 0.1 mm option, green; 0.13 mm (5.1181 mil) other colors; normal dam 0.32 mm (12.5984 mil) green, 0.35 mm (13.7795 mil) other colors"
},
"maskSliver": {
"mm": 0.1,
"mil": 3.94,
"condition": "min solder mask dam, green, 0.1 mm option"
},
"silkLineWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "min silkscreen trace width; min character height 0.5842 mm (23 mil)"
},
"silkToCopper": {
"mm": 0.1524,
"mil": 6.0,
"condition": "pad to silkscreen clearance"
},
"minCopperClearance": {
"mm": 0.3048,
"mil": 12.0,
"condition": "plated holes to traces; inner trace to plated holes 0.2 mm (7.874 mil)"
},
"boardThicknessOptionsMm": [
0.6,
0.8,
1.0,
1.2,
1.6,
2.0,
2.5,
3.0
],
"copperWeightOptionsOz": [
1,
2,
3
],
"surfaceFinishes": [
"HASL",
"HASL lead-free",
"ENIG",
"OSP",
"Hard Gold"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 500.0
},
"notes": "Trace width/spacing by copper weight: 1 oz: 4/4, 5/5, or 6/6 mil options (0.1016/0.127/0.1524 mm); 2 oz: 10/10 mil (0.254 mm); 3 oz: 15/15 mil (0.381 mm). RF coil designs require 6/6 mil but select 4/4 mil option. Min board size 10 x 10 mm. Drill ranges: NPTH 0.2 to 6.3 mm, PTH 0.2 to 5.8 mm, via holes 0.2 to 0.5 mm (vias 0.3 mm and smaller guarantee full mask tenting). Min via pad not published directly, min annular ring 0.1 mm implies pad = drill + 0.2 mm. Min plated slot 0.65 mm, non-plated slot 0.8 mm. BGA pitch guidance: 0.45 mm pitch with 6/6 mil, 0.35 mm with 5/5 mil, 0.25 mm with 4/4 mil.",
"sources": [
{
"url": "https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification",
"dateRead": "2026-09-03"
},
{
"url": "https://www.seeedstudio.com/fusion_pcb.html",
"dateRead": "2026-09-03"
}
],
"processDetail": "standard (Quickturn) PCB"
},
{
"process": "standard",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "outer layer, 1 oz copper, 4/4 mil option"
},
"minSpacing": {
"mm": 0.1016,
"mil": 4.0,
"condition": "outer layer, 1 oz copper, 4/4 mil option"
},
"minDrill": {
"mm": 0.2,
"mil": 7.87
},
"minVia": {
"drillMm": 0.2,
"drillMil": 7.87,
"padMm": 0.4,
"padMil": 15.75
},
"annularRing": {
"viaMm": 0.1,
"viaMil": 3.94,
"note": "vias, PTH is 0.152 mm (5.9843 mil)"
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 11.81
},
"holeToHole": {
"mm": 0.3,
"mil": 11.81,
"condition": "vias, PTH is 0.45 mm (17.7165 mil)"
},
"maskExpansion": {
"mm": 0.1,
"mil": 3.94,
"condition": "solder mask dam, 0.1 mm option, green; 0.13 mm (5.1181 mil) other colors"
},
"maskSliver": {
"mm": 0.1,
"mil": 3.94,
"condition": "min solder mask dam, green, 0.1 mm option"
},
"silkLineWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "min silkscreen trace width; min character height 0.5842 mm (23 mil)"
},
"silkToCopper": {
"mm": 0.1524,
"mil": 6.0,
"condition": "pad to silkscreen clearance"
},
"minCopperClearance": {
"mm": 0.3048,
"mil": 12.0,
"condition": "plated holes to traces; min distance inner trace to plated holes 0.2 mm (7.874 mil)"
},
"boardThicknessOptionsMm": [
0.8,
1.0,
1.2,
1.6,
2.0,
2.5,
3.0
],
"copperWeightOptionsOz": [
1,
2,
3
],
"surfaceFinishes": [
"HASL",
"HASL lead-free",
"ENIG",
"OSP",
"Hard Gold"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 500.0
},
"notes": "Minimum trace width in inner layers for 4 layer boards: 0.15 mm (6 mil). Inner layer base copper 0.017 mm (0.5 oz), outer 0.035 to 0.07 mm (1 to 2 oz). Same trace width/spacing options by copper weight as 2 layer: 1 oz 4/4, 5/5, 6/6 mil; 2 oz 10/10 mil; 3 oz 15/15 mil. Min board size 10 x 10 mm. Castellated holes (plated half-holes) min 0.50 mm.",
"sources": [
{
"url": "https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification",
"dateRead": "2026-09-03"
}
],
"processDetail": "standard (Quickturn) PCB"
},
{
"process": "standard",
"layerCount": 6,
"minTraceWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "outer layer, 1 oz copper, 4/4 mil option"
},
"minSpacing": {
"mm": 0.1016,
"mil": 4.0,
"condition": "outer layer, 1 oz copper, 4/4 mil option"
},
"minDrill": {
"mm": 0.2,
"mil": 7.87
},
"minVia": {
"drillMm": 0.2,
"drillMil": 7.87,
"padMm": 0.4,
"padMil": 15.75
},
"annularRing": {
"viaMm": 0.1,
"viaMil": 3.94,
"note": "vias, PTH is 0.152 mm (5.9843 mil)"
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 11.81
},
"holeToHole": {
"mm": 0.3,
"mil": 11.81,
"condition": "vias, PTH is 0.45 mm (17.7165 mil)"
},
"maskExpansion": {
"mm": 0.1,
"mil": 3.94,
"condition": "solder mask dam, 0.1 mm option, green; 0.13 mm (5.1181 mil) other colors"
},
"maskSliver": {
"mm": 0.1,
"mil": 3.94,
"condition": "min solder mask dam, green, 0.1 mm option"
},
"silkLineWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "min silkscreen trace width; min character height 0.5842 mm (23 mil)"
},
"silkToCopper": {
"mm": 0.1524,
"mil": 6.0,
"condition": "pad to silkscreen clearance"
},
"minCopperClearance": {
"mm": 0.3048,
"mil": 12.0,
"condition": "plated holes to traces"
},
"boardThicknessOptionsMm": [
1.0,
1.2,
1.6,
2.0,
2.5,
3.0
],
"copperWeightOptionsOz": [
1,
2,
3
],
"surfaceFinishes": [
"HASL",
"HASL lead-free",
"ENIG",
"OSP",
"Hard Gold"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 500.0
},
"notes": "Seeed standard service supports 1 to 6 layers (layers table extends to 16). Board thickness options listed are for 6 and 8 layer boards. Inner layer trace width limit not separately published for 6 layer; 4 layer value is 0.15 mm (6 mil).",
"sources": [
{
"url": "https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification",
"dateRead": "2026-09-03"
}
],
"processDetail": "standard (Quickturn) PCB"
},
{
"process": "advanced",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.127,
"mil": 5.0,
"condition": "outer layer, 1 oz copper"
},
"minSpacing": {
"mm": 0.127,
"mil": 5.0,
"condition": "outer layer, 1 oz copper"
},
"minDrill": {
"mm": 0.1,
"mil": 3.94,
"condition": "minimum mechanical via diameter, PCB thickness 0.6 mm or less"
},
"minVia": {
"drillMm": 0.1,
"drillMil": 3.94,
"padMm": 0.3032,
"padMil": 11.94
},
"annularRing": {
"viaMm": 0.1016,
"viaMil": 4.0,
"note": "vias, through-holes 0.2032 mm (8 mil)"
},
"copperToBoardEdge": null,
"holeToHole": {
"mm": 0.2286,
"mil": 9.0,
"condition": "via wall to via wall, different nets, prototype; 12 mil (0.3048 mm) mass production"
},
"maskExpansion": {
"mm": 0.08,
"mil": 3.15,
"condition": "min solder mask dam, green; 0.12 mm (4.7244 mil) other colors"
},
"maskSliver": {
"mm": 0.08,
"mil": 3.15,
"condition": "min solder mask dam, green"
},
"silkLineWidth": null,
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.2286,
"mil": 9.0,
"condition": "via to traces inner layers, prototype, different nets; 12 mil (0.3048 mm) mass production"
},
"boardThicknessOptionsMm": [],
"copperWeightOptionsOz": [
0.33,
0.5,
1,
2,
3,
4,
5,
6
],
"surfaceFinishes": [
"HASL",
"HASL lead-free",
"ENIG",
"Hard Gold",
"Immersion Tin",
"Immersion Silver",
"OSP"
],
"maxBoardSize": {
"xMm": null,
"yMm": null
},
"notes": "Outer layer trace/spacing by copper weight: 1/3 oz 3/3 mil (0.0762 mm), 0.5 oz 4/4 mil (0.1016 mm), 1 oz 5/5 mil (0.127 mm), 2 oz 6/8 mil (0.1524/0.2032 mm), 3 oz 7/10 mil (0.1778/0.254 mm), 4 oz 8/13 mil (0.2032/0.3302 mm), 5 oz 10/16 mil (0.254/0.4064 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). Board thickness rigid 0.2 to 8.0 mm. Min castellated hole diameter 0.35 mm. Plugged vias finished diameter 0.15 to 0.8 mm. HDI stacks 1+n+1, 1+1+n+1+1, 2+n+2. Outline, V-cut and milling slot tolerance 0.10 mm. Solder mask colors include purple, matte green, customized. Board size limits not published on this page.",
"sources": [
{
"url": "https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification",
"dateRead": "2026-09-03"
}
],
"processDetail": "advanced PCB"
},
{
"process": "advanced",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "inner layer, 1 oz copper"
},
"minSpacing": {
"mm": 0.1016,
"mil": 4.0,
"condition": "inner layer, 1 oz copper"
},
"minDrill": {
"mm": 0.1,
"mil": 3.94,
"condition": "minimum mechanical via diameter, PCB thickness 0.6 mm or less"
},
"minVia": {
"drillMm": 0.1,
"drillMil": 3.94,
"padMm": 0.3032,
"padMil": 11.94
},
"annularRing": {
"viaMm": 0.1016,
"viaMil": 4.0,
"note": "vias, through-holes 0.2032 mm (8 mil)"
},
"copperToBoardEdge": null,
"holeToHole": {
"mm": 0.2286,
"mil": 9.0,
"condition": "via wall to via wall, different nets, prototype; 12 mil (0.3048 mm) mass production"
},
"maskExpansion": {
"mm": 0.08,
"mil": 3.15,
"condition": "min solder mask dam, green; 0.12 mm (4.7244 mil) other colors"
},
"maskSliver": {
"mm": 0.08,
"mil": 3.15,
"condition": "min solder mask dam, green"
},
"silkLineWidth": null,
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.2286,
"mil": 9.0,
"condition": "via to traces inner layers, prototype, different nets; 12 mil (0.3048 mm) mass production"
},
"boardThicknessOptionsMm": [],
"copperWeightOptionsOz": [
0.5,
1,
2,
3,
4,
5,
6
],
"surfaceFinishes": [
"HASL",
"HASL lead-free",
"ENIG",
"Hard Gold",
"Immersion Tin",
"Immersion Silver",
"OSP"
],
"maxBoardSize": {
"xMm": null,
"yMm": null
},
"notes": "Inner layer trace/spacing by copper weight: 0.5 oz 3/3 mil (0.0762 mm), 1 oz 4/4 mil (0.1016 mm), 2 oz 5/6 mil (0.127/0.1524 mm), 3 oz 7/9 mil (0.1778/0.2286 mm), 4 oz 8/12 mil (0.2032/0.3048 mm), 5 oz 10/15 mil (0.254/0.381 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). For outer layer values see the 2 layer entry. FR4 1 to 30 layers, rigid-flex up to 36 rigid layers, board thickness rigid 0.2 to 8.0 mm. Back drilling diameter 0.5 to 6.3 mm, depth tolerance 0.10 mm. Min BGA pad diameter 7 mil (0.1778 mm) with 4/4 mil trace/spacing.",
"sources": [
{
"url": "https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification",
"dateRead": "2026-09-03"
}
],
"processDetail": "advanced PCB"
}
]
}