skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
main
John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
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{
"vendor": "JLCPCB",
"vendorSlug": "jlcpcb",
"vendorUrl": null,
"records": [
{
"process": "standard",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.1,
"mil": 4.0,
"condition": "1 oz copper outer layer"
},
"minSpacing": {
"mm": 0.1,
"mil": 4.0,
"condition": "1 oz copper, different nets"
},
"minDrill": {
"mm": 0.15,
"mil": 5.91
},
"minVia": {
"drillMm": 0.15,
"drillMil": 5.91,
"padMm": 0.25,
"padMil": 9.84
},
"annularRing": {
"viaMm": 0.18,
"viaMil": 7.09,
"note": "PTH, 1 oz outer, absolute minimum, recommended 0.25 mm"
},
"copperToBoardEdge": {
"mm": 0.2,
"mil": 7.87,
"condition": "routed edge, 0.4 mm for V-cut edge"
},
"holeToHole": {
"mm": 0.2,
"mil": 7.87,
"condition": "via hole to via hole, pad hole to pad hole is 0.45 mm"
},
"maskExpansion": {
"mm": 0.0,
"mil": 0.0,
"condition": "LDI, 1:1 pad to soldermask opening since June 2025"
},
"maskSliver": {
"mm": 0.1,
"mil": 3.94,
"condition": "1 oz, soldermask bridge, green/red/yellow/blue/purple, 0.13 mm for black/white, 0.20 mm for 2 oz"
},
"silkLineWidth": {
"mm": 0.15,
"mil": 5.91
},
"silkToCopper": {
"mm": 0.15,
"mil": 5.91,
"condition": "pad to silkscreen minimum distance"
},
"minCopperClearance": {
"mm": 0.1,
"mil": 3.94,
"condition": "different nets, 1 oz"
},
"boardThicknessOptionsMm": [
0.4,
0.6,
0.8,
1.0,
1.2,
1.6,
2.0
],
"copperWeightOptionsOz": [
1,
2,
2.5,
3.5,
4.5
],
"surfaceFinishes": [
"HASL leaded",
"HASL lead-free",
"ENIG"
],
"maxBoardSize": {
"xMm": 670.0,
"yMm": 600.0,
"condition": "absolute max 1020 x 600 mm for 2 layer FR4"
},
"notes": "2 oz: min trace/spacing 0.16/0.16 mm (6.5/6.5 mil). 2.5 oz: 0.2/0.2 mm (8/8 mil). 3.5 oz: 0.25/0.25 mm (10/10 mil). 4.5 oz: 0.3/0.3 mm (12/12 mil). Min drill 0.15 mm costs more. Via diameter should be 0.1 mm (0.15 mm preferred) larger than via hole, preferred min via hole 0.2 mm. PTH annular ring 2 oz: 0.254 mm or above. NPTH pad annular ring 0.45 mm recommended. Min NPTH 0.5 mm. Min plated slot width 0.5 mm. Pad to track clearance 0.1 mm. SMD pad to pad clearance different nets 0.15 mm. Via hole to track 0.2 mm, PTH to track 0.28 mm (0.35 recommended), NPTH to track 0.2 mm. Same-net track spacing 0.25 mm. Min silk text height 1.0 mm (40 mil). Soldermask opening to neighboring trace clearance 0.09 mm. Trace width tolerance plus/minus 20 percent.",
"sources": [
{
"url": "https://jlcpcb.com/capabilities/pcb-capabilities",
"dateRead": "2026-09-03"
}
]
},
{
"process": "standard",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.09,
"mil": 3.5,
"condition": "1 oz copper outer layer, 3 mil acceptable in BGA fan-outs"
},
"minSpacing": {
"mm": 0.09,
"mil": 3.5,
"condition": "1 oz copper, different nets"
},
"minDrill": {
"mm": 0.15,
"mil": 5.91
},
"minVia": {
"drillMm": 0.15,
"drillMil": 5.91,
"padMm": 0.25,
"padMil": 9.84
},
"annularRing": {
"viaMm": 0.15,
"viaMil": 5.91,
"note": "PTH, 1 oz outer, absolute minimum, recommended 0.20 mm"
},
"copperToBoardEdge": {
"mm": 0.2,
"mil": 7.87,
"condition": "routed edge, 0.4 mm for V-cut edge"
},
"holeToHole": {
"mm": 0.2,
"mil": 7.87,
"condition": "via hole to via hole, pad hole to pad hole is 0.45 mm"
},
"maskExpansion": {
"mm": 0.0,
"mil": 0.0,
"condition": "LDI, 1:1 pad to soldermask opening since June 2025"
},
"maskSliver": {
"mm": 0.1,
"mil": 3.94,
"condition": "1 oz, soldermask bridge, green/red/yellow/blue/purple, 0.13 mm for black/white, 0.20 mm for 2 oz"
},
"silkLineWidth": {
"mm": 0.15,
"mil": 5.91
},
"silkToCopper": {
"mm": 0.15,
"mil": 5.91,
"condition": "pad to silkscreen minimum distance"
},
"minCopperClearance": {
"mm": 0.09,
"mil": 3.5,
"condition": "different nets, 1 oz, 0.09 mm locally for BGA pads"
},
"boardThicknessOptionsMm": [
0.4,
0.6,
0.8,
1.0,
1.2,
1.6,
2.0
],
"copperWeightOptionsOz": [
1,
2
],
"surfaceFinishes": [
"HASL leaded",
"HASL lead-free",
"ENIG"
],
"maxBoardSize": {
"xMm": 663.0,
"yMm": 593.0,
"condition": "absolute max 1016 x 596 mm for 4 layer FR4"
},
"notes": "Same source page as 2 layer, multilayer column. Inner layer copper 0.5/1/2 oz, 0.5 oz default. Inner layer via hole to copper clearance 0.2 mm, inner PTH pad hole to copper clearance 0.3 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Min plated slot width 0.35 mm multilayer. Controlled impedance available. Blind/buried vias not supported, through holes only.",
"sources": [
{
"url": "https://jlcpcb.com/capabilities/pcb-capabilities",
"dateRead": "2026-09-03"
}
]
},
{
"process": "standard",
"layerCount": 6,
"minTraceWidth": {
"mm": 0.09,
"mil": 3.5,
"condition": "1 oz copper outer layer, 3 mil acceptable in BGA fan-outs"
},
"minSpacing": {
"mm": 0.09,
"mil": 3.5,
"condition": "1 oz copper, different nets"
},
"minDrill": {
"mm": 0.15,
"mil": 5.91
},
"minVia": {
"drillMm": 0.15,
"drillMil": 5.91,
"padMm": 0.25,
"padMil": 9.84
},
"annularRing": {
"viaMm": 0.15,
"viaMil": 5.91,
"note": "PTH, 1 oz outer, absolute minimum, recommended 0.20 mm"
},
"copperToBoardEdge": {
"mm": 0.2,
"mil": 7.87,
"condition": "routed edge, 0.4 mm for V-cut edge"
},
"holeToHole": {
"mm": 0.2,
"mil": 7.87,
"condition": "via hole to via hole, pad hole to pad hole is 0.45 mm"
},
"maskExpansion": {
"mm": 0.0,
"mil": 0.0,
"condition": "LDI, 1:1 pad to soldermask opening since June 2025"
},
"maskSliver": {
"mm": 0.1,
"mil": 3.94,
"condition": "1 oz, soldermask bridge, green/red/yellow/blue/purple, 0.13 mm for black/white, 0.20 mm for 2 oz"
},
"silkLineWidth": {
"mm": 0.15,
"mil": 5.91
},
"silkToCopper": {
"mm": 0.15,
"mil": 5.91,
"condition": "pad to silkscreen minimum distance"
},
"minCopperClearance": {
"mm": 0.09,
"mil": 3.5,
"condition": "different nets, 1 oz"
},
"boardThicknessOptionsMm": [
0.4,
0.6,
0.8,
1.0,
1.2,
1.6,
2.0
],
"copperWeightOptionsOz": [
1,
2
],
"surfaceFinishes": [
"ENIG"
],
"maxBoardSize": {
"xMm": 656.0,
"yMm": 586.0,
"condition": "6 layer and above"
},
"notes": "Same source page as 2 layer, multilayer column. 6 layer and above boards only have ENIG surface finish. Via-in-pad epoxy filled and capped is the default process for 6 layer and above boards, compatible with via diameters 0.15 to 0.55 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Backdrill supported on 4 to 32 layer FR4, thickness 0.8 mm or more.",
"sources": [
{
"url": "https://jlcpcb.com/capabilities/pcb-capabilities",
"dateRead": "2026-09-03"
}
]
}
],
"unreachable": [
"https://jlcpcb.com/help/article/59-How-to-Set-Up-DRC-in-EAGLE (JS-rendered help article, no DRC numbers retrievable)"
]
}