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PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
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{
"vendor": "Eurocircuits",
"vendorSlug": "eurocircuits",
"vendorUrl": null,
"records": [
{
"process": "proto",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.15,
"mil": 5.91,
"condition": "all services, pattern class 6"
},
"minSpacing": {
"mm": 0.15,
"mil": 5.91,
"condition": "track to track, pattern class 6; class 5 is 0.175 mm (6.8898 mil), class 7 is 0.125 mm (4.9213 mil)"
},
"minDrill": {
"mm": 0.25,
"mil": 9.84,
"condition": "min finished PTH hole; NPTH 0.35 mm (13.7795 mil)"
},
"minVia": {
"drillMm": 0.25,
"drillMil": 9.84,
"padMm": 0.6,
"padMil": 23.62
},
"annularRing": {
"viaMm": 0.125,
"viaMil": 4.92,
"note": "outer and inner, plated holes, pattern class 6; recommended NPTH annular ring 0.30 mm (11.811 mil)"
},
"copperToBoardEdge": {
"mm": 0.25,
"mil": 9.84,
"condition": "outer layers, routed; inner layers 0.40 mm (15.748 mil)"
},
"holeToHole": {
"mm": 0.25,
"mil": 9.84,
"condition": "drill to drill, edge to edge of TOOLSIZE"
},
"maskExpansion": {
"mm": 0.03,
"mil": 1.18,
"condition": "mask annular ring MAR, LDI colors green, black, red, blue; PI white or transparent 0.10 mm (3.937 mil); minimum SM opening 0.40 mm (15.748 mil)"
},
"maskSliver": {
"mm": 0.075,
"mil": 2.95,
"condition": "mask segment MSM, LDI colors; PI white or transparent 0.130 mm (5.1181 mil)"
},
"silkLineWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "min legend line width; min text height 1.00 mm (39.5 mil)"
},
"silkToCopper": {
"mm": 0.1,
"mil": 3.94,
"condition": "legend to exposed copper or surface finished copper; also 0.10 mm to holes and cutouts"
},
"minCopperClearance": {
"mm": 0.15,
"mil": 5.91,
"condition": "different nets, pattern class 6 (standard); IPI clearance unconnected hole to copper 0.200 mm (7.874 mil)"
},
"boardThicknessOptionsMm": [
1.55
],
"copperWeightOptionsOz": [
0.5,
1
],
"surfaceFinishes": [
"ENIG",
"LF HAL"
],
"maxBoardSize": {
"xMm": 580.0,
"yMm": 425.0
},
"notes": "Min board 20 x 20 mm. Base copper foil: outer layers 18 \u00b5m (0.5 oz), inner layers 35 \u00b5m (1 oz). Minimum pad diameter: PTH is finished hole plus 0.350 mm on outer and inner layers, NPTH is finished hole plus 0.250 mm. Tool size equals finished PTH hole size plus 0.10 mm (4 mil), NPTH tool size equals finished size. Drill bits in 0.05 mm increments. Standard PTH hole tolerance plus/minus 0.10 mm (0.20 mm range) for holes 4 mm or less, NPTH plus/minus 0.05 mm. Holes with finished size 0.45 mm or smaller are defined as via holes. Pattern class 5 (all services): track/gap 0.175 mm (6.8898 mil), OAR/IAR 0.150 mm (5.9055 mil), IPI 0.225 mm (8.8583 mil). Legend to board edge: 0.250 mm routing, 0.450 mm scoring. Soldermask design rules LDI: pad to pad 0.135 mm (5.315 mil), track to pad 0.090 mm (3.5433 mil); PI colors: pad to pad 0.330 mm (12.9921 mil), track to pad 0.190 mm (7.4803 mil). Mask overlap clearance MOC: LDI 0.060 mm (2.3622 mil), PI 0.090 mm (3.5433 mil).",
"sources": [
{
"url": "https://www.eurocircuits.com/services/pcb-proto/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/drilled-holes/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/soldermask/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/legend-print/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/copper-layers/",
"dateRead": "2026-09-03"
}
],
"processDetail": "PCB proto"
},
{
"process": "proto",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.15,
"mil": 5.91,
"condition": "outer and inner layers, pattern class 6"
},
"minSpacing": {
"mm": 0.15,
"mil": 5.91,
"condition": "pattern class 6; class 5 is 0.175 mm (6.8898 mil)"
},
"minDrill": {
"mm": 0.25,
"mil": 9.84,
"condition": "min finished PTH hole; NPTH 0.35 mm (13.7795 mil)"
},
"minVia": {
"drillMm": 0.25,
"drillMil": 9.84,
"padMm": 0.6,
"padMil": 23.62
},
"annularRing": {
"viaMm": 0.125,
"viaMil": 4.92,
"note": "outer and inner, plated holes, pattern class 6; recommended NPTH 0.30 mm (11.811 mil)"
},
"copperToBoardEdge": {
"mm": 0.25,
"mil": 9.84,
"condition": "outer layers, routed; inner layers 0.40 mm (15.748 mil)"
},
"holeToHole": {
"mm": 0.25,
"mil": 9.84,
"condition": "drill to drill, edge to edge of TOOLSIZE"
},
"maskExpansion": {
"mm": 0.03,
"mil": 1.18,
"condition": "MAR, LDI colors; PI white or transparent 0.10 mm (3.937 mil); min SM opening 0.40 mm (15.748 mil)"
},
"maskSliver": {
"mm": 0.075,
"mil": 2.95,
"condition": "MSM, LDI colors; PI white or transparent 0.130 mm (5.1181 mil)"
},
"silkLineWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "min legend line width; min text height 1.00 mm (39.5 mil)"
},
"silkToCopper": {
"mm": 0.1,
"mil": 3.94,
"condition": "legend to exposed copper"
},
"minCopperClearance": {
"mm": 0.15,
"mil": 5.91,
"condition": "different nets, pattern class 6; IPI 0.200 mm (7.874 mil)"
},
"boardThicknessOptionsMm": [
1.55
],
"copperWeightOptionsOz": [
0.5,
1
],
"surfaceFinishes": [
"ENIG",
"LF HAL"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 425.0
},
"notes": "4 layer max board size 500 x 425 mm. Same build parameters as 2 layer. Blind and buried vias not available in PCB proto.",
"sources": [
{
"url": "https://www.eurocircuits.com/services/pcb-proto/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",
"dateRead": "2026-09-03"
}
],
"processDetail": "PCB proto"
},
{
"process": "standard",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "pooling; non-pooling 0.090 mm (3.5433 mil)"
},
"minSpacing": {
"mm": 0.1,
"mil": 3.94,
"condition": "pooling; non-pooling 0.090 mm (3.5433 mil); pattern class table: class 6 track/gap 0.150 mm (5.9055 mil), class 7 0.125 mm (4.9213 mil), class 8 0.100 mm (3.937 mil), class 9 0.090 mm (3.5433 mil), class 5 0.175 mm (6.8898 mil)"
},
"minDrill": {
"mm": 0.1,
"mil": 3.94,
"condition": "min finished PTH hole; NPTH 0.20 mm (7.874 mil); classification drill classes by service: class A (all services) PTH 0.50 mm (19.685 mil), class B PTH 0.35 mm (13.7795 mil), class C PTH 0.25 mm (9.8425 mil), class D PTH 0.15 mm (5.9055 mil), class E PTH 0.10 mm (3.937 mil)"
},
"minVia": {
"drillMm": 0.1,
"drillMil": 3.94,
"padMm": 0.4,
"padMil": 15.75
},
"annularRing": {
"viaMm": 0.125,
"viaMil": 4.92,
"note": "outer and inner, plated holes, pattern class 6; class 8 is 0.100 mm (3.937 mil); recommended NPTH 0.30 mm (11.811 mil)"
},
"copperToBoardEdge": {
"mm": 0.25,
"mil": 9.84,
"condition": "outer layers routed; inner layers routed 0.40 mm (15.748 mil); V-cut 0.45 mm (17.7165 mil) outer and inner"
},
"holeToHole": {
"mm": 0.25,
"mil": 9.84,
"condition": "drill to drill, edge to edge of TOOLSIZE"
},
"maskExpansion": {
"mm": 0.03,
"mil": 1.18,
"condition": "MAR, LDI colors; PI white or transparent 0.10 mm (3.937 mil); min SM opening 0.40 mm (15.748 mil)"
},
"maskSliver": {
"mm": 0.075,
"mil": 2.95,
"condition": "MSM, LDI colors; PI white or transparent 0.130 mm (5.1181 mil)"
},
"silkLineWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "min legend line width; min text height 1.00 mm (39.5 mil)"
},
"silkToCopper": {
"mm": 0.1,
"mil": 3.94,
"condition": "legend to exposed copper"
},
"minCopperClearance": {
"mm": 0.15,
"mil": 5.91,
"condition": "different nets, pattern class 6 (default); class 5 0.175 mm (6.8898 mil), class 7 0.125 mm (4.9213 mil), class 8 0.100 mm (3.937 mil), class 9 0.090 mm (3.5433 mil); IPI unconnected hole to copper 0.200 mm (7.874 mil)"
},
"boardThicknessOptionsMm": [
1.0,
1.55,
2.4
],
"copperWeightOptionsOz": [
0.5,
0.67,
1,
2
],
"surfaceFinishes": [
"ENIG",
"LF HAL",
"Immersion Silver"
],
"maxBoardSize": {
"xMm": 580.0,
"yMm": 425.0
},
"notes": "Min board 5 x 5 mm. Base copper foil pooling 2 layer: 12 \u00b5m (0.33 oz), 18 \u00b5m (0.5 oz), 35 \u00b5m (1 oz), 70 \u00b5m (2 oz); inner layers 18 \u00b5m and 35 \u00b5m. Minimum pad diameter: outer PTH finished hole plus 0.300 mm, outer NPTH plus 0.200 mm, inner PTH plus 0.350 mm, inner NPTH plus 0.250 mm. Classification min pattern values also limited by base copper foil: 12 \u00b5m 0.090 mm (3.5 mil), 18 \u00b5m 0.100 mm (4 mil), 35 \u00b5m 0.125 mm (5 mil), 70 \u00b5m 0.200 mm (8 mil), 105 \u00b5m 0.250 mm (10 mil), for both outer and inner layers. Drill class minimum TOOLSIZE: class A 0.60 mm (23.622 mil), B 0.45 mm (17.7165 mil), C 0.35 mm (13.7795 mil), D 0.25 mm (9.8425 mil), E 0.20 mm (7.874 mil); max board thickness per drill class: A and B 3.20 mm, C 2.40 mm, D 2.00 mm, E 1.60 mm; aspect ratio 1:8. TOOLSIZE equals finished PTH size plus 0.10 mm (4 mil). Soldermask colors pooling: green, blue, black, white, red; non-pooling transparent. Legend white one or both sides, non-pooling black and white.",
"sources": [
{
"url": "https://www.eurocircuits.com/services/standard-pool/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png",
"dateRead": "2026-09-03"
}
],
"processDetail": "STANDARD pool"
},
{
"process": "standard",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "pooling; non-pooling 0.090 mm (3.5433 mil); inner layer same classification values"
},
"minSpacing": {
"mm": 0.1,
"mil": 3.94,
"condition": "pooling; non-pooling 0.090 mm (3.5433 mil); pattern class 6 is 0.150 mm (5.9055 mil)"
},
"minDrill": {
"mm": 0.1,
"mil": 3.94,
"condition": "min finished PTH hole; NPTH 0.20 mm (7.874 mil); drill classes A 0.50 mm to E 0.10 mm finished PTH"
},
"minVia": {
"drillMm": 0.1,
"drillMil": 3.94,
"padMm": 0.4,
"padMil": 15.75
},
"annularRing": {
"viaMm": 0.125,
"viaMil": 4.92,
"note": "outer and inner, plated holes, pattern class 6; recommended NPTH 0.30 mm (11.811 mil)"
},
"copperToBoardEdge": {
"mm": 0.25,
"mil": 9.84,
"condition": "outer layers routed; inner layers routed 0.40 mm (15.748 mil); V-cut 0.45 mm (17.7165 mil)"
},
"holeToHole": {
"mm": 0.25,
"mil": 9.84,
"condition": "drill to drill, edge to edge of TOOLSIZE"
},
"maskExpansion": {
"mm": 0.03,
"mil": 1.18,
"condition": "MAR, LDI colors; PI 0.10 mm (3.937 mil); min SM opening 0.40 mm (15.748 mil)"
},
"maskSliver": {
"mm": 0.075,
"mil": 2.95,
"condition": "MSM, LDI colors; PI 0.130 mm (5.1181 mil)"
},
"silkLineWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "min legend line width; min text height 1.00 mm (39.5 mil)"
},
"silkToCopper": {
"mm": 0.1,
"mil": 3.94,
"condition": "legend to exposed copper"
},
"minCopperClearance": {
"mm": 0.15,
"mil": 5.91,
"condition": "different nets, pattern class 6; IPI 0.200 mm (7.874 mil)"
},
"boardThicknessOptionsMm": [
1.0,
1.55
],
"copperWeightOptionsOz": [
0.5,
0.67,
1,
2
],
"surfaceFinishes": [
"ENIG",
"LF HAL",
"Immersion Silver"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 425.0
},
"notes": "4 layer pooling board thickness 1.00 mm; 1.55 mm pooling for 6 to 16 layers. Multilayer max dimension 500 x 425 mm. Standard buildups pooled, 8 predefined non-pooling builds; blind and buried vias non-pooling specials. Base copper inner layers pooling 18 \u00b5m and 35 \u00b5m.",
"sources": [
{
"url": "https://www.eurocircuits.com/services/standard-pool/",
"dateRead": "2026-09-03"
},
{
"url": "https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/",
"dateRead": "2026-09-03"
}
],
"processDetail": "STANDARD pool"
},
{
"process": "standard",
"layerCount": 6,
"minTraceWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "pooling; non-pooling 0.090 mm (3.5433 mil)"
},
"minSpacing": {
"mm": 0.1,
"mil": 3.94,
"condition": "pooling; non-pooling 0.090 mm (3.5433 mil)"
},
"minDrill": {
"mm": 0.1,
"mil": 3.94,
"condition": "min finished PTH hole; NPTH 0.20 mm (7.874 mil)"
},
"minVia": {
"drillMm": 0.1,
"drillMil": 3.94,
"padMm": 0.4,
"padMil": 15.75
},
"annularRing": {
"viaMm": 0.125,
"viaMil": 4.92,
"note": "outer and inner, plated holes, pattern class 6"
},
"copperToBoardEdge": {
"mm": 0.25,
"mil": 9.84,
"condition": "outer layers routed; inner 0.40 mm (15.748 mil); V-cut 0.45 mm (17.7165 mil)"
},
"holeToHole": {
"mm": 0.25,
"mil": 9.84,
"condition": "drill to drill, edge to edge of TOOLSIZE"
},
"maskExpansion": {
"mm": 0.03,
"mil": 1.18,
"condition": "MAR, LDI colors; PI 0.10 mm (3.937 mil)"
},
"maskSliver": {
"mm": 0.075,
"mil": 2.95,
"condition": "MSM, LDI colors; PI 0.130 mm (5.1181 mil)"
},
"silkLineWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "min legend line width"
},
"silkToCopper": {
"mm": 0.1,
"mil": 3.94,
"condition": "legend to exposed copper"
},
"minCopperClearance": {
"mm": 0.15,
"mil": 5.91,
"condition": "different nets, pattern class 6; IPI 0.200 mm (7.874 mil)"
},
"boardThicknessOptionsMm": [
1.55
],
"copperWeightOptionsOz": [
0.5,
0.67,
1,
2
],
"surfaceFinishes": [
"ENIG",
"LF HAL",
"Immersion Silver"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 425.0
},
"notes": "6 and 8 layers pooling in STANDARD pool; 10 to 16 layers non-pooling. Pooling board thickness for multilayers 6 layers and above is 1.55 mm. Same pattern and drill classification system applies.",
"sources": [
{
"url": "https://www.eurocircuits.com/services/standard-pool/",
"dateRead": "2026-09-03"
}
],
"processDetail": "STANDARD pool"
}
],
"unreachable": [
"https://www.eurocircuits.com/our-services/eurocircuits-pcb-specifications/ (404)"
]
}