skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
main
John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
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{
"vendor": "ALLPCB",
"vendorSlug": "allpcb",
"vendorUrl": null,
"records": [
{
"process": "standard",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.1,
"mil": 3.94,
"condition": "all copper weights; vendor suggests 6mil (0.15mm) or more to save cost"
},
"minSpacing": {
"mm": 0.1,
"mil": 3.94,
"condition": "all copper weights; vendor suggests 6mil (0.15mm) or more to save cost"
},
"minDrill": {
"mm": 0.2,
"mil": 7.87
},
"minVia": null,
"annularRing": {
"viaMm": 0.153,
"viaMil": 6.02
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 11.81
},
"holeToHole": {
"mm": 0.2032,
"mil": 8.0
},
"maskExpansion": null,
"maskSliver": {
"mm": 0.1,
"mil": 3.94
},
"silkLineWidth": {
"mm": 0.15,
"mil": 5.91
},
"silkToCopper": null,
"minCopperClearance": null,
"boardThicknessOptionsMm": [
0.4,
3.2
],
"copperWeightOptionsOz": [
0.5,
1,
2
],
"surfaceFinishes": [
"HASL",
"Immersion Gold",
"Immersion Silver",
"Immersion Tin",
"OSP",
"Hard Gold plating",
"Soft Gold plating",
"NiPdAu"
],
"maxBoardSize": {
"xMm": 506,
"yMm": 580
},
"notes": "Single published limit set covers 1 to 14 layers, so this entry also applies to 4 and 6 layer boards. Board thickness is a continuous 0.4 to 3.2mm range. Copper: outer 1oz to 2oz (35 to 70um), inner 0.5oz to 2oz (18 to 70um). Min dimension 80x80mm. Drill range 0.2 to 6.5mm, finished CNC hole 0.2 to 6.5mm, hole size tolerance \u00b10.075mm. Copper to V-cut line 0.4mm (15.748mil) for panelized boards. Via space same net 8mil (0.2032mm), different nets 17mil (0.4318mm), component vias different nets 24mil (0.6096mm). Annular ring 6mil or larger where surrounded by traces. Min slot width 0.6mm, finished slot 0.45mm for HASL and 0.5mm for other finishes. Board thickness to via diameter ratio 6:1, 7:1 to 8:1 adds a fabrication day. Min character height 0.8mm (31.4961mil), width to height ratio 1:5. Mask sliver recorded from solder mask bridge value 0.1mm (price may rise).",
"sources": [
{
"url": "https://www.allpcb.com/standard_pcb_manufacturing_capability.html",
"dateRead": "2026-09-03"
}
]
},
{
"process": "advanced",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.076,
"mil": 3.0,
"condition": "1oz copper"
},
"minSpacing": {
"mm": 0.076,
"mil": 3.0,
"condition": "1oz copper"
},
"minDrill": {
"mm": 0.15,
"mil": 5.91
},
"minVia": {
"drillMm": 0.2,
"drillMil": 7.87,
"padMm": 0.5,
"padMil": 19.68
},
"annularRing": {
"viaMm": 0.18,
"viaMil": 7.09
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 11.81
},
"holeToHole": null,
"maskExpansion": null,
"maskSliver": {
"mm": 0.075,
"mil": 2.95
},
"silkLineWidth": {
"mm": 0.1,
"mil": 3.94
},
"silkToCopper": {
"mm": 0.15,
"mil": 5.91
},
"minCopperClearance": {
"mm": 0.1,
"mil": 3.94,
"condition": "pad edge to trace edge; BGA pad to trace 0.075mm (2.9528mil)"
},
"boardThicknessOptionsMm": [
0.4,
4.0
],
"copperWeightOptionsOz": [
1,
2,
3,
4,
5,
6
],
"surfaceFinishes": [
"Bare Copper",
"OSP",
"HASL With Lead",
"HASL Lead-free",
"Immersion Gold",
"Immersion Tin",
"Immersion Silver",
"Nickel Palladium Gold",
"OSP plus Selective Immersion Gold",
"Lead-free HASL plus Selective Immersion Gold",
"Lead-free HASL plus Selective Gold Plating"
],
"maxBoardSize": {
"xMm": 630,
"yMm": 520
},
"notes": "Double-side board via/pad: 0.2mm inner diameter, 0.5mm outer diameter; outer diameter must be 0.1mm larger than inner, 0.15mm preferred; preferred min via hole 0.2mm. Trace/spacing by copper weight: 1oz 0.076mm, 2oz 0.14mm (5.5118mil), 3oz 0.2mm (7.874mil), 4oz 0.25mm (9.8425mil), 5oz 0.35mm (13.7795mil), 6oz 0.45mm (17.7165mil). Trace width tolerance \u00b120%. Annular ring: plated DIP holes 1oz recommended 0.2mm, limit 0.18mm; non-plated DIP holes recommended 0.4mm (15.748mil). Min plated slot 0.7mm (27.5591mil), min non-plated slot 0.8mm (31.4961mil). Board thickness to min plated hole ratio 10:1. Plated half hole diameter 0.4mm or more, spacing 0.35mm (13.7795mil). Min single PCB size 10x5mm. Copper to board edge 0.3mm at non-stamp-hole panel areas; V-cut line to copper 0.4mm. Mask sliver recorded from min solder bridge width: green 0.075mm, other colors 0.125mm (4.9213mil). Silk text height 0.75mm (29.5276mil). BGA pad diameter 0.2mm or more. Edge rail 4mm or more.",
"sources": [
{
"url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",
"dateRead": "2026-09-03"
}
]
},
{
"process": "advanced",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.076,
"mil": 3.0,
"condition": "1oz copper"
},
"minSpacing": {
"mm": 0.076,
"mil": 3.0,
"condition": "1oz copper"
},
"minDrill": {
"mm": 0.15,
"mil": 5.91
},
"minVia": {
"drillMm": 0.15,
"drillMil": 5.91,
"padMm": 0.25,
"padMil": 9.84
},
"annularRing": {
"viaMm": 0.18,
"viaMil": 7.09
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 11.81
},
"holeToHole": null,
"maskExpansion": null,
"maskSliver": {
"mm": 0.075,
"mil": 2.95
},
"silkLineWidth": {
"mm": 0.1,
"mil": 3.94
},
"silkToCopper": {
"mm": 0.15,
"mil": 5.91
},
"minCopperClearance": {
"mm": 0.1,
"mil": 3.94,
"condition": "pad edge to trace edge; BGA pad to trace 0.075mm (2.9528mil)"
},
"boardThicknessOptionsMm": [
0.4,
4.0
],
"copperWeightOptionsOz": [
1,
2,
3,
4,
5,
6
],
"surfaceFinishes": [
"Bare Copper",
"OSP",
"HASL With Lead",
"HASL Lead-free",
"Immersion Gold",
"Immersion Tin",
"Immersion Silver",
"Nickel Palladium Gold",
"OSP plus Selective Immersion Gold",
"Lead-free HASL plus Selective Immersion Gold",
"Lead-free HASL plus Selective Gold Plating"
],
"maxBoardSize": {
"xMm": 630,
"yMm": 520
},
"notes": "Multi-layer board via/pad: 0.15mm inner diameter, 0.25mm outer diameter. Other limits as 2 layer entry.",
"sources": [
{
"url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",
"dateRead": "2026-09-03"
}
]
},
{
"process": "advanced",
"layerCount": 6,
"minTraceWidth": {
"mm": 0.076,
"mil": 3.0,
"condition": "1oz copper"
},
"minSpacing": {
"mm": 0.076,
"mil": 3.0,
"condition": "1oz copper"
},
"minDrill": {
"mm": 0.15,
"mil": 5.91
},
"minVia": {
"drillMm": 0.15,
"drillMil": 5.91,
"padMm": 0.25,
"padMil": 9.84
},
"annularRing": {
"viaMm": 0.18,
"viaMil": 7.09
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 11.81
},
"holeToHole": null,
"maskExpansion": null,
"maskSliver": {
"mm": 0.075,
"mil": 2.95
},
"silkLineWidth": {
"mm": 0.1,
"mil": 3.94
},
"silkToCopper": {
"mm": 0.15,
"mil": 5.91
},
"minCopperClearance": {
"mm": 0.1,
"mil": 3.94,
"condition": "pad edge to trace edge; BGA pad to trace 0.075mm (2.9528mil)"
},
"boardThicknessOptionsMm": [
0.6,
4.0
],
"copperWeightOptionsOz": [
1,
2,
3,
4,
5,
6
],
"surfaceFinishes": [
"Bare Copper",
"OSP",
"HASL With Lead",
"HASL Lead-free",
"Immersion Gold",
"Immersion Tin",
"Immersion Silver",
"Nickel Palladium Gold",
"OSP plus Selective Immersion Gold",
"Lead-free HASL plus Selective Immersion Gold",
"Lead-free HASL plus Selective Gold Plating"
],
"maxBoardSize": {
"xMm": 630,
"yMm": 520
},
"notes": "6 layer board thickness range 0.6 to 4.0mm, differs from 2 and 4 layer range 0.4 to 4.0mm. Other limits as 4 layer entry.",
"sources": [
{
"url": "https://www.allpcb.com/advanced_pcb_manufacturing_capability.html",
"dateRead": "2026-09-03"
}
]
}
]
}