skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
main
John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262
{
"vendor": "Aisler",
"vendorSlug": "aisler",
"vendorUrl": null,
"records": [
{
"process": "enig",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.125,
"mil": 5.0,
"condition": "Cu 35um (1oz), ENIG finish"
},
"minSpacing": {
"mm": 0.125,
"mil": 5.0,
"condition": "Cu 35um (1oz), ENIG finish"
},
"minDrill": {
"mm": 0.25,
"mil": 10.0,
"condition": "via drill, drills up to 0.45mm are treated as vias and not adjusted; PTH drills start at 0.5mm"
},
"minVia": {
"drillMm": 0.25,
"drillMil": 10.0,
"padMm": 0.45,
"padMil": 17.72
},
"annularRing": {
"viaMm": 0.1,
"viaMil": 4.0,
"note": "via, PTH annular ring 300um (12 mil)"
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 12.0
},
"holeToHole": {
"mm": 0.3,
"mil": 12.0
},
"maskExpansion": {
"mm": 0.05,
"mil": 2.0,
"condition": "suggested soldermask expansion"
},
"maskSliver": {
"mm": 0.1,
"mil": 4.0,
"condition": "minimum soldermask dam, recommended but not required for ENIG"
},
"silkLineWidth": {
"mm": 0.15,
"mil": 6.0
},
"silkToCopper": {
"mm": 0.125,
"mil": 5.0,
"condition": "silkscreen to pad, silkscreen on pads not supported"
},
"minCopperClearance": {
"mm": 0.125,
"mil": 5.0,
"condition": "different nets, copper to copper"
},
"boardThicknessOptionsMm": [
1.6
],
"copperWeightOptionsOz": [
1
],
"surfaceFinishes": [
"ENIG"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 500.0
},
"notes": "Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Min SMD pad size 200um (8 mil). Copper to NPTH clearance 250um (10 mil), copper to NPTH slot clearance 300um (12 mil) for slots under and over 1.8mm. PTH drill range 0.5mm to 5.6mm, PTH annular ring 300um. Via drill range 0.25mm to 0.45mm, via annular ring 100um. NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm, PTH slot annular ring 300um. Min silkscreen text height 800um (32 mil). Max silkscreen coverage 25% per board side. Castellated edges supported free of charge. Green soldermask (Peters Elpemer AS 2467), buried, blind, micro, and tented vias not supported. Via pad diameter not published.",
"sources": [
{
"url": "https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732",
"dateRead": "2026-09-03"
}
],
"processDetail": "Beautiful Boards 2 Layer 1.6mm ENIG (35um copper)"
},
{
"process": "hasl",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.2,
"mil": 8.0,
"condition": "Cu 35um (1oz), HASL finish"
},
"minSpacing": {
"mm": 0.15,
"mil": 6.0,
"condition": "Cu 35um (1oz), HASL finish"
},
"minDrill": {
"mm": 0.3,
"mil": 12.0,
"condition": "via drill, PTH drills start at 0.5mm"
},
"minVia": {
"drillMm": 0.3,
"drillMil": 12.0,
"padMm": 0.7,
"padMil": 27.56
},
"annularRing": {
"viaMm": 0.2,
"viaMil": 8.0,
"note": "via, 175um absolute minimum to compensate for drill enlargement up to 0.45mm; PTH annular ring 300um (12 mil)"
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 12.0
},
"holeToHole": {
"mm": 0.3,
"mil": 12.0
},
"maskExpansion": {
"mm": 0.05,
"mil": 2.0,
"condition": "suggested soldermask expansion"
},
"maskSliver": {
"mm": 0.1,
"mil": 4.0,
"condition": "minimum soldermask dam, required for HASL"
},
"silkLineWidth": {
"mm": 0.15,
"mil": 6.0
},
"silkToCopper": {
"mm": 0.125,
"mil": 5.0,
"condition": "silkscreen to pad, silkscreen on pads not supported"
},
"minCopperClearance": {
"mm": 0.15,
"mil": 6.0,
"condition": "different nets, copper to copper"
},
"boardThicknessOptionsMm": [
1.6
],
"copperWeightOptionsOz": [
1
],
"surfaceFinishes": [
"HASL"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 500.0
},
"notes": "Lead-free HASL. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Via drill range 0.3mm to 0.45mm, drill may be enlarged up to 0.45mm. PTH drill range 0.5mm to 5.6mm, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges not supported with HASL. Green soldermask (Peters Elpemer AS 2467). Via pad diameter not published.",
"sources": [
{
"url": "https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735",
"dateRead": "2026-09-03"
}
],
"processDetail": "Beautiful Boards 2 Layer 1.6mm HASL (35um copper)"
},
{
"process": "enig",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.125,
"mil": 5.0,
"condition": "Cu 35um (1oz), ENIG finish"
},
"minSpacing": {
"mm": 0.125,
"mil": 5.0,
"condition": "Cu 35um (1oz), ENIG finish"
},
"minDrill": {
"mm": 0.25,
"mil": 10.0,
"condition": "via drill, PTH drills start at 0.5mm"
},
"minVia": {
"drillMm": 0.25,
"drillMil": 10.0,
"padMm": 0.45,
"padMil": 17.72
},
"annularRing": {
"viaMm": 0.1,
"viaMil": 4.0,
"note": "via, PTH annular ring 300um (12 mil)"
},
"copperToBoardEdge": {
"mm": 0.3,
"mil": 12.0
},
"holeToHole": {
"mm": 0.3,
"mil": 12.0
},
"maskExpansion": {
"mm": 0.05,
"mil": 2.0,
"condition": "suggested soldermask expansion"
},
"maskSliver": {
"mm": 0.1,
"mil": 4.0,
"condition": "minimum soldermask dam, recommended but not required for ENIG"
},
"silkLineWidth": {
"mm": 0.15,
"mil": 6.0
},
"silkToCopper": {
"mm": 0.125,
"mil": 5.0,
"condition": "silkscreen to pad, silkscreen on pads not supported"
},
"minCopperClearance": {
"mm": 0.125,
"mil": 5.0,
"condition": "different nets, copper to copper"
},
"boardThicknessOptionsMm": [
0.8,
1.6
],
"copperWeightOptionsOz": [
1
],
"surfaceFinishes": [
"ENIG"
],
"maxBoardSize": {
"xMm": 500.0,
"yMm": 500.0
},
"notes": "Source page states rules are valid for both 0.8mm and 1.6mm PCB thickness. Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. PTH drill range 0.5mm to 5.6mm, via drill range 0.25mm to 0.45mm, via annular ring 100um, NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm. Min silkscreen text height 800um (32 mil). Castellated edges supported free of charge. Green soldermask. Via pad diameter not published.",
"sources": [
{
"url": "https://community.aisler.net/t/4-layer-35-m-enig-design-rules/3733",
"dateRead": "2026-09-03"
}
],
"processDetail": "Beautiful Boards 4 Layer ENIG (35um copper, 0.8mm and 1.6mm)"
}
],
"unreachable": [
"https://aisler.net/about/manufacturing (404)",
"https://aisler.net/pages/technical-capabilities (returned login page)",
"https://aisler.net/capabilities (404)"
]
}