skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
main
John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
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{
"vendor": "Advanced Circuits (4PCB)",
"vendorSlug": "advanced-circuits-4pcb",
"vendorUrl": null,
"records": [
{
"process": "standard",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.127,
"mil": 5.0,
"condition": "outer trace, standard spec"
},
"minSpacing": {
"mm": 0.127,
"mil": 5.0,
"condition": "standard spec trace/space 5/5 mils"
},
"minDrill": {
"mm": 0.254,
"mil": 10.0
},
"minVia": {
"drillMm": 0.254,
"drillMil": 10.0,
"padMm": null,
"padMil": null
},
"annularRing": null,
"copperToBoardEdge": null,
"holeToHole": null,
"maskExpansion": null,
"maskSliver": null,
"silkLineWidth": null,
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.127,
"mil": 5.0,
"condition": "different nets"
},
"boardThicknessOptionsMm": [
0.7874,
1.5748,
2.3622,
3.175
],
"copperWeightOptionsOz": [
1,
2
],
"surfaceFinishes": [
"Lead-Free HAL"
],
"maxBoardSize": {
"xMm": 406.4,
"yMm": 558.8
},
"notes": "Standard spec: FR-4, 0 to 12 layers, IPC Class 2, quantity 1 to 10000 plus, turn time same day to 5 day. Hole tolerance plus or minus 0.005 in (0.127 mm). Rout tolerance plus or minus 0.010 in (0.254 mm). Solder mask LPI green, legend white. Board thickness options 0.031, 0.062, 0.093, 0.125 in. Standard finish pricing assumes lead-free HAL; ENIG or immersion silver at no extra cost if HAL unavailable. Same spec applies to 2 and 4 layer; page does not differentiate by layer count below 12.",
"sources": [
{
"url": "https://www.4pcb.com/laminate-material-vendors.html",
"dateRead": "2026-09-03"
}
],
"processDetail": "standard (Standard Technology PCBs)"
},
{
"process": "standard",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.127,
"mil": 5.0,
"condition": "outer trace, standard spec"
},
"minSpacing": {
"mm": 0.127,
"mil": 5.0,
"condition": "standard spec trace/space 5/5 mils"
},
"minDrill": {
"mm": 0.254,
"mil": 10.0
},
"minVia": {
"drillMm": 0.254,
"drillMil": 10.0,
"padMm": null,
"padMil": null
},
"annularRing": null,
"copperToBoardEdge": null,
"holeToHole": null,
"maskExpansion": null,
"maskSliver": null,
"silkLineWidth": null,
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.127,
"mil": 5.0,
"condition": "different nets"
},
"boardThicknessOptionsMm": [
0.7874,
1.5748,
2.3622,
3.175
],
"copperWeightOptionsOz": [
1,
2
],
"surfaceFinishes": [
"Lead-Free HAL"
],
"maxBoardSize": {
"xMm": 406.4,
"yMm": 558.8
},
"notes": "Same standard spec as 2 layer. Typical 4-layer stackup published at 0.020, 0.031, 0.062, 0.093, 0.125 in finished thickness with 1 oz copper, max board size 16 x 22 in for 0.031 to 0.093 in, 14 x 20 in (355.6 x 508 mm) at 0.125 in.",
"sources": [
{
"url": "https://www.4pcb.com/laminate-material-vendors.html",
"dateRead": "2026-09-03"
}
],
"processDetail": "standard (Standard Technology PCBs)"
},
{
"process": "advanced-standard",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.1397,
"mil": 5.5,
"condition": "outer layer, 1 oz Cu base; other weights: 0.0762 mm (3 mil) at 1/4 and 3/8 oz base, 0.1143 mm (4.5 mil) at 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)"
},
"minSpacing": {
"mm": 0.1397,
"mil": 5.5,
"condition": "outer layer trace to trace, 1 oz Cu base; 0.0762 mm (3 mil) at 1/4, 3/8, 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)"
},
"minDrill": {
"mm": 0.1499,
"mil": 5.9,
"condition": "smallest mechanical PTH via, aspect ratio driven; smallest component PTH 0.381 mm (15 mil)"
},
"minVia": {
"drillMm": 0.1499,
"drillMil": 5.9,
"padMm": 0.5309,
"padMil": 20.9
},
"annularRing": {
"viaMm": 0.1905,
"viaMil": 7.5,
"note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"
},
"copperToBoardEdge": {
"mm": 0.254,
"mil": 10.0
},
"holeToHole": {
"mm": 0.3048,
"mil": 12.0,
"condition": "minimum hole to hole edge for PTH"
},
"maskExpansion": {
"mm": 0.0762,
"mil": 3.0,
"condition": "solder mask clearance to pad, i.e. annular ring"
},
"maskSliver": {
"mm": 0.1016,
"mil": 4.0,
"condition": "solder mask web width over laminate between pads; 0.0762 mm (3 mil) over copper"
},
"silkLineWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "minimum, white only, height 15 to 20 mil; standard silkscreen 5 mil width, 25 to 30 mil height"
},
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.1397,
"mil": 5.5,
"condition": "different nets, outer layer 1 oz Cu base"
},
"boardThicknessOptionsMm": [],
"copperWeightOptionsOz": [
0.25,
0.375,
0.5,
1,
2,
3,
4
],
"surfaceFinishes": [],
"maxBoardSize": {
"xMm": 406.4,
"yMm": 558.8
},
"notes": "Capabilities table is per facility and per tier; this object is Santa Clara, CA, Standard column. Min board thickness 0.01 in (0.254 mm), max board thickness 0.25 in (6.35 mm). PTH tolerance plus or minus 0.003 in (0.0762 mm). Drill to copper for PTH 0.01 in (0.254 mm). Minimum pad 0.015 in (0.381 mm), minimum isolated pad 0.01 in (0.254 mm). Min copper sliver between antipads 0.005 in (0.127 mm). Aspect ratio plated through holes 10:1 for drilled greater than 0.020 in, 10:1 for 0.010 to 0.019 in. Other facilities differ, e.g. Maple Grove MN standard outer 1 oz trace width is 0.1016 mm (4 mil), smallest mech via 0.0043 in (0.1092 mm).",
"sources": [
{
"url": "https://www.4pcb.com/pcb-capabilities.html",
"dateRead": "2026-09-03"
}
],
"processDetail": "advanced capabilities, Santa Clara CA facility, Standard tier"
},
{
"process": "advanced-standard",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.1397,
"mil": 5.5,
"condition": "outer layer, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil); inner 1/2 oz: 0.0889 mm (3.5 mil)"
},
"minSpacing": {
"mm": 0.1397,
"mil": 5.5,
"condition": "outer layer trace to trace, 1 oz Cu base; inner layer 1 oz: 0.1143 mm (4.5 mil)"
},
"minDrill": {
"mm": 0.1499,
"mil": 5.9,
"condition": "smallest mechanical PTH via, aspect ratio driven; smallest component PTH 0.381 mm (15 mil)"
},
"minVia": {
"drillMm": 0.1499,
"drillMil": 5.9,
"padMm": 0.5309,
"padMil": 20.9
},
"annularRing": {
"viaMm": 0.1905,
"viaMil": 7.5,
"note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"
},
"copperToBoardEdge": {
"mm": 0.254,
"mil": 10.0
},
"holeToHole": {
"mm": 0.3048,
"mil": 12.0,
"condition": "minimum hole to hole edge for PTH"
},
"maskExpansion": {
"mm": 0.0762,
"mil": 3.0,
"condition": "solder mask clearance to pad, i.e. annular ring"
},
"maskSliver": {
"mm": 0.1016,
"mil": 4.0,
"condition": "solder mask web width over laminate between pads; 0.0762 mm (3 mil) over copper"
},
"silkLineWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "minimum, white only, height 15 to 20 mil; standard silkscreen 5 mil width, 25 to 30 mil height"
},
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.1397,
"mil": 5.5,
"condition": "different nets, outer layer 1 oz Cu base"
},
"boardThicknessOptionsMm": [],
"copperWeightOptionsOz": [
0.25,
0.375,
0.5,
1,
2,
3,
4
],
"surfaceFinishes": [],
"maxBoardSize": {
"xMm": 406.4,
"yMm": 558.8
},
"notes": "Same capabilities table values as 2 layer; buried vias mechanical drill minimum 0.0059 in (0.1499 mm), blind vias mechanical 0.0059 in, laser drilled blind via minimum 0.004 in (0.1016 mm).",
"sources": [
{
"url": "https://www.4pcb.com/pcb-capabilities.html",
"dateRead": "2026-09-03"
}
],
"processDetail": "advanced capabilities, Santa Clara CA facility, Standard tier"
},
{
"process": "advanced",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "outer layer, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz base, 0.0762 mm (3 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz; inner 1 oz: 0.0889 mm (3.5 mil)"
},
"minSpacing": {
"mm": 0.1016,
"mil": 4.0,
"condition": "outer layer trace to trace, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz, 0.0635 mm (2.5 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz"
},
"minDrill": {
"mm": 0.127,
"mil": 5.0,
"condition": "smallest mechanical PTH via, aspect ratio driven"
},
"minVia": {
"drillMm": 0.127,
"drillMil": 5.0,
"padMm": 0.508,
"padMil": 20.0
},
"annularRing": {
"viaMm": 0.1905,
"viaMil": 7.5,
"note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"
},
"copperToBoardEdge": {
"mm": 0.2032,
"mil": 8.0
},
"holeToHole": {
"mm": 0.254,
"mil": 10.0,
"condition": "minimum hole to hole edge for PTH"
},
"maskExpansion": {
"mm": 0.0508,
"mil": 2.0,
"condition": "solder mask clearance to pad, i.e. annular ring"
},
"maskSliver": {
"mm": 0.0762,
"mil": 3.0,
"condition": "solder mask web width over laminate between pads; 0.0508 mm (2 mil) over copper"
},
"silkLineWidth": {
"mm": 0.0762,
"mil": 3.0,
"condition": "minimum, white only, height 15 to 20 mil"
},
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.1016,
"mil": 4.0,
"condition": "different nets, outer layer 1 oz Cu base"
},
"boardThicknessOptionsMm": [],
"copperWeightOptionsOz": [
0.25,
0.375,
0.5,
1,
2,
3,
4
],
"surfaceFinishes": [],
"maxBoardSize": {
"xMm": 482.6,
"yMm": 558.8
},
"notes": "Santa Clara CA, Advanced tier. Max board size 19 x 22 in. Min board thickness 0.008 in (0.2032 mm). PTH tolerance plus or minus 0.002 in (0.0508 mm). Minimum pad 0.01 in (0.254 mm). Min outer layer trace for filled and plated over vias 0.004 in (0.1016 mm). Aspect ratio PTH 12:1.",
"sources": [
{
"url": "https://www.4pcb.com/pcb-capabilities.html",
"dateRead": "2026-09-03"
}
],
"processDetail": "advanced capabilities, Santa Clara CA facility, Advanced tier"
},
{
"process": "advanced",
"layerCount": 4,
"minTraceWidth": {
"mm": 0.1016,
"mil": 4.0,
"condition": "outer layer, 1 oz Cu base; inner 1 oz: 0.0889 mm (3.5 mil)"
},
"minSpacing": {
"mm": 0.1016,
"mil": 4.0,
"condition": "outer layer trace to trace, 1 oz Cu base; inner 1 oz: 0.1016 mm (4 mil)"
},
"minDrill": {
"mm": 0.127,
"mil": 5.0,
"condition": "smallest mechanical PTH via, aspect ratio driven"
},
"minVia": {
"drillMm": 0.127,
"drillMil": 5.0,
"padMm": 0.508,
"padMil": 20.0
},
"annularRing": {
"viaMm": 0.1905,
"viaMil": 7.5,
"note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"
},
"copperToBoardEdge": {
"mm": 0.2032,
"mil": 8.0
},
"holeToHole": {
"mm": 0.254,
"mil": 10.0,
"condition": "minimum hole to hole edge for PTH"
},
"maskExpansion": {
"mm": 0.0508,
"mil": 2.0,
"condition": "solder mask clearance to pad, i.e. annular ring"
},
"maskSliver": {
"mm": 0.0762,
"mil": 3.0,
"condition": "solder mask web width over laminate between pads; 0.0508 mm (2 mil) over copper"
},
"silkLineWidth": {
"mm": 0.0762,
"mil": 3.0,
"condition": "minimum, white only, height 15 to 20 mil"
},
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.1016,
"mil": 4.0,
"condition": "different nets, outer layer 1 oz Cu base"
},
"boardThicknessOptionsMm": [],
"copperWeightOptionsOz": [
0.25,
0.375,
0.5,
1,
2,
3,
4
],
"surfaceFinishes": [],
"maxBoardSize": {
"xMm": 482.6,
"yMm": 558.8
},
"notes": "Same Advanced tier values as 2 layer for this facility.",
"sources": [
{
"url": "https://www.4pcb.com/pcb-capabilities.html",
"dateRead": "2026-09-03"
}
],
"processDetail": "advanced capabilities, Santa Clara CA facility, Advanced tier"
},
{
"process": "development-npi",
"layerCount": 2,
"minTraceWidth": {
"mm": 0.0762,
"mil": 3.0,
"condition": "outer layer, 1 oz Cu base; 0.0381 mm (1.5 mil) at 1/4 and 3/8 oz base, 0.0559 mm (2.2 mil) at 1/2 oz, 0.1016 mm (4 mil) at 2 oz, 0.1524 mm (6 mil) at 3 oz; inner 1 oz: 0.0762 mm (3 mil)"
},
"minSpacing": {
"mm": 0.0762,
"mil": 3.0,
"condition": "outer layer trace to trace, 1 oz Cu base; 0.0381 mm (1.5 mil) at 1/4 and 3/8 oz, 0.0559 mm (2.2 mil) at 1/2 oz, 0.127 mm (5 mil) at 2 oz, 0.1524 mm (6 mil) at 3 oz"
},
"minDrill": null,
"minVia": null,
"annularRing": {
"viaMm": 0.1905,
"viaMil": 7.5,
"note": "derived from published no-breakout rule: pad = drill + 0.015 in, annular ring = 0.0075 in"
},
"copperToBoardEdge": {
"mm": 0.127,
"mil": 5.0
},
"holeToHole": {
"mm": 0.2032,
"mil": 8.0,
"condition": "minimum hole to hole edge for PTH"
},
"maskExpansion": {
"mm": 0.0254,
"mil": 1.0,
"condition": "solder mask clearance to pad, i.e. annular ring"
},
"maskSliver": {
"mm": 0.0508,
"mil": 2.0,
"condition": "solder mask web width over laminate between pads and over copper"
},
"silkLineWidth": null,
"silkToCopper": null,
"minCopperClearance": {
"mm": 0.0762,
"mil": 3.0,
"condition": "different nets, outer layer 1 oz Cu base"
},
"boardThicknessOptionsMm": [],
"copperWeightOptionsOz": [
0.5,
1,
2,
3
],
"surfaceFinishes": [],
"maxBoardSize": {
"xMm": null,
"yMm": null
},
"notes": "Santa Clara CA, Development (NPI) tier; maximum board size not published for this tier. Min board thickness 0.008 in (0.2032 mm). PTH tolerance plus or minus 0.0015 in (0.0381 mm). Minimum pad 0.008 in (0.2032 mm). Min outer layer trace for filled and plated over vias 0.003 in (0.0762 mm). Aspect ratio PTH 14:1. Smallest PTH fillable and plated over 0.005 in (0.127 mm).",
"sources": [
{
"url": "https://www.4pcb.com/pcb-capabilities.html",
"dateRead": "2026-09-03"
}
],
"processDetail": "advanced capabilities, Santa Clara CA facility, Development (NPI) tier"
}
]
}