PCB Design Rules - kicad/sierra-circuits-4L.kicad_dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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(version 1)

# Sierra Circuits 4-layer design rules (standard process)
# 
# Min trace width: 0.1016 mm (4.0 mil) - STANDARD tier
# Min spacing: 0.1016 mm (4.0 mil) - STANDARD tier
# Min drill: 0.15 mm (5.9 mil)
# Min via: 0.15 mm hole / 0.4547 mm pad
# Annular ring: via 0.0254 mm
# Copper to board edge: 0.254 mm
# Board thickness options: 0.254 mm, 7.62 mm
# Copper weight options: 4 oz
# Surface finishes: HASL, Lead-Free HASL, OSP (Shikoku F2), OSP (Entek), ENIG, Immersion Silver, Electrolytic Soft Gold, Electrolytic Hard Gold, Selective Gold
# Max board size: 304.8 x 457.2 mm
# 
# Same STANDARD tier table as 2-layer, Sierra does not publish separate 4-layer limits on this page. Blind and buried vias available. Controlled impedance tolerance 10 percent STANDARD tier.
# 
# Sources:
# - https://www.protoexpress.com/products/rigid-pcb/ (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.1016mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.1016mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.15mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.4547mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.254mm))
  (condition "A.type == 'track'"))