skill

PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

pcbdesign-rulesdrcfabricationjlcpcbpcbwayfusionkicadaltiumedrukicad_dru
Overview Files Skills Discover Packages Releases Dependencies Issues1 Breadcrumbs Pull Requests1 Activity
main
pcb-design-rules / kicad / seeed-fusion-advanced-2L.kicad_dru
HistoryDownload
John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago
1234567891011121314151617181920212223242526272829303132333435
(version 1)

# Seeed Fusion 2-layer design rules (advanced process)
# 
# Min trace width: 0.127 mm (5.0 mil) - outer layer, 1 oz copper
# Min spacing: 0.127 mm (5.0 mil) - outer layer, 1 oz copper
# Min drill: 0.1 mm (3.94 mil)
# Min via: 0.1 mm hole / 0.3032 mm pad
# Annular ring: via 0.1016 mm
# Hole to hole: 0.2286 mm
# Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz
# Surface finishes: HASL, HASL lead-free, ENIG, Hard Gold, Immersion Tin, Immersion Silver, OSP
# Max board size: n/a x n/a mm
# 
# Outer layer trace/spacing by copper weight: 1/3 oz 3/3 mil (0.0762 mm), 0.5 oz 4/4 mil (0.1016 mm), 1 oz 5/5 mil (0.127 mm), 2 oz 6/8 mil (0.1524/0.2032 mm), 3 oz 7/10 mil (0.1778/0.254 mm), 4 oz 8/13 mil (0.2032/0.3302 mm), 5 oz 10/16 mil (0.254/0.4064 mm), 6 oz 12/18 mil (0.3048/0.4572 mm). Board thickness rigid 0.2 to 8.0 mm. Min castellated hole diameter 0.35 mm. Plugged vias finished diameter 0.15 to 0.8 mm. HDI stacks 1+n+1, 1+1+n+1+1, 2+n+2. Outline, V-cut and milling slot tolerance 0.10 mm. Solder mask colors include purple, matte green, customized. Board size limits not published on this page.
# 
# Sources:
# - https://support.seeed.cc/portal/en/kb/articles/fusion-advanced-pcb-specification (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.127mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.127mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.1mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.3032mm))
  (condition "A.type == 'via'"))