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PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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pcb-design-rules / kicad / seeed-fusion-6L.kicad_dru
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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago
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(version 1)

# Seeed Fusion 6-layer design rules (standard process)
# 
# Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option
# Min spacing: 0.1016 mm (4.0 mil) - outer layer, 1 oz copper, 4/4 mil option
# Min drill: 0.2 mm (7.87 mil)
# Min via: 0.2 mm hole / 0.4 mm pad
# Annular ring: via 0.1 mm
# Copper to board edge: 0.3 mm
# Hole to hole: 0.3 mm
# Board thickness options: 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm
# Copper weight options: 1 oz, 2 oz, 3 oz
# Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold
# Max board size: 500 x 500 mm
# 
# Seeed standard service supports 1 to 6 layers (layers table extends to 16). Board thickness options listed are for 6 and 8 layer boards. Inner layer trace width limit not separately published for 6 layer; 4 layer value is 0.15 mm (6 mil).
# 
# Sources:
# - https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.1016mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.1016mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.2mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.4mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.3mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.1016mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))