PCB Design Rules - kicad/pcbway-advanced-2L.kicad_dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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(version 1)

# PCBWay 2-layer design rules (advanced process)
# 
# Min trace width: 0.0508 mm (2.0 mil) - outer layer, 1/3 oz base copper, only part of traces on the board, not whole board; capabilities table advanced outer 0.5oz: 4mil with parts 3.5mil (0.0889mm) in BGA chip area
# Min spacing: 0.0508 mm (2.0 mil) - outer layer, 1/3 oz base copper, partial traces only; capabilities table advanced outer 0.5oz: 4mil, parts 3.5mil
# Min drill: 0.15 mm (5.91 mil)
# Min via: 0.15 mm hole / 0.3024 mm pad
# Annular ring: via 0.0762 mm
# Copper to board edge: 0.2 mm
# Hole to hole: 0.3556 mm
# Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm
# Copper weight options: 0.33 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz, 6 oz, 8 oz
# Surface finishes: ENIG, HAL, HAL lead free, OSP, Immersion Sn, Immersion silver, Plating hard gold, Plating silver
# Max board size: 609 x 889 mm
# 
# Advanced page does not distinguish limits by layer count for 2 layers. Min board thickness 0.25mm. Max aspect ratio 20:1. Max layer count 64. Min BGA pad diameter 8mil, min BGA pitch 0.4mm. Min base copper 1/3 oz, max finished copper 8 oz. Min insulating layer thickness 2mil. Max board thickness 4.5mm.
# 
# Sources:
# - https://www.pcbway.com/advanced-pcb-capabilities.html (read 2026-09-03)
# - https://www.pcbway.com/capabilities.html (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.0508mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.0508mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.15mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.3024mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.2mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.15mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))