PCB Design Rules - kicad/pcbway-6L.kicad_dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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(version 1)

# PCBWay 6-layer design rules (standard process)
# 
# Min trace width: 0.1016 mm (4.0 mil) - inner layer, 1oz (35um) copper, before compensation; outer layer 1oz: 5mil
# Min spacing: 0.127 mm (5.0 mil) - inner layer, 1oz (35um) copper, before compensation; inner 2oz: 8mil, 3oz: 11mil. Outer layer 1oz: 6mil
# Min drill: 0.2 mm (7.87 mil)
# Min via: 0.2 mm hole / 0.454 mm pad
# Annular ring: via 0.127 mm
# Copper to board edge: 0.25 mm
# Hole to hole: 0.2794 mm
# Board thickness options: 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm
# Copper weight options: 0.5 oz, 1 oz, 1.5 oz, 2 oz, 3 oz, 4 oz
# Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin
# Max board size: 508 x 600 mm
# 
# Min board thickness 0.9mm, max board thickness 3.2mm. Min inner layer isolation ring (hole to inner layer conductor, before compensation) 8mil (0.2032mm). Inner layer copper weight options 1oz or 1.5oz. Max aspect ratio 8:1.
# 
# Sources:
# - https://www.pcbway.com/capabilities.html (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.1016mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.127mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.2mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.454mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.25mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.15mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))