skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
main
John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
(version 1)
# OSH Park 6-layer design rules (standard process)
#
# Min trace width: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper
# Min spacing: 0.127 mm (5.0 mil) - 1oz outer, 0.5oz inner copper
# Min drill: 0.2032 mm (8.0 mil)
# Min via: 0.2032 mm hole / 0.4064 mm pad
# Annular ring: via 0.1016 mm
# Copper to board edge: 0.381 mm
# Hole to hole: 0.127 mm
# Board thickness options: 1.6 mm
# Copper weight options: 1 oz
# Surface finishes: ENIG
# Max board size: 406.4 x 558.8 mm
#
# Summary values from the services index page. Blind and buried vias not supported.
#
# Sources:
# - https://docs.oshpark.com/services/ (read 2026-09-03)
(rule "min-track-width"
(constraint track_width (min 0.127mm))
(layer "*.Cu")
(condition "A.type == 'track'"))
(rule "min-clearance"
(constraint clearance (min 0.127mm))
(condition "A.type == 'track' && B.type == 'track'"))
(rule "min-hole"
(constraint hole (min 0.2032mm))
(condition "A.type == 'pad' || A.type == 'via'"))
(rule "min-via-diameter"
(constraint via_diameter (min 0.4064mm))
(condition "A.type == 'via'"))
(rule "min-edge-clearance"
(constraint edge_clearance (min 0.381mm))
(condition "A.type == 'track'"))
(rule "min-silk-thickness"
(constraint text_thickness (min 0.127mm))
(layer "*.SilkS")
(condition "A.type == 'text' || A.type == 'graphic'"))