skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
(version 1)
# NextPCB 4-layer design rules (standard process)
#
# Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper
# Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper
# Min drill: 0.15 mm (5.91 mil)
# Min via: 0.2 mm hole / 0.3278 mm pad
# Annular ring: via 0.0889 mm
# Copper to board edge: 0.2 mm
# Hole to hole: 0.3048 mm
# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm
# Copper weight options: 0.5 oz, 1 oz, 2 oz
# Max board size: 1500 x 500 mm
#
# Same published limits as 2 layer except max dimension 1500x500mm for 4 layers. Trace/spacing by copper weight: 0.5oz inner 2.5mil/3mil, 1oz outer 3mil/3mil, 2oz outer 5.5mil/5.5mil.
#
# Sources:
# - https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)
(rule "min-track-width"
(constraint track_width (min 0.0635mm))
(layer "*.Cu")
(condition "A.type == 'track'"))
(rule "min-clearance"
(constraint clearance (min 0.0762mm))
(condition "A.type == 'track' && B.type == 'track'"))
(rule "min-hole"
(constraint hole (min 0.15mm))
(condition "A.type == 'pad' || A.type == 'via'"))
(rule "min-via-diameter"
(constraint via_diameter (min 0.3278mm))
(condition "A.type == 'via'"))
(rule "min-edge-clearance"
(constraint edge_clearance (min 0.2mm))
(condition "A.type == 'track'"))
(rule "min-silk-thickness"
(constraint text_thickness (min 0.0762mm))
(layer "*.SilkS")
(condition "A.type == 'text' || A.type == 'graphic'"))