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PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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pcb-design-rules / kicad / nextpcb-2L.kicad_dru
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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago
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(version 1)

# NextPCB 2-layer design rules (standard process)
# 
# Min trace width: 0.0635 mm (2.5 mil) - H/HOZ 0.5oz inner layer copper
# Min spacing: 0.0762 mm (3.0 mil) - H/HOZ 0.5oz inner layer copper
# Min drill: 0.15 mm (5.91 mil)
# Min via: 0.2 mm hole / 0.3278 mm pad
# Annular ring: via 0.0889 mm
# Copper to board edge: 0.2 mm
# Hole to hole: 0.3048 mm
# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm, 3.2 mm
# Copper weight options: 0.5 oz, 1 oz, 2 oz
# Max board size: 1500 x 600 mm
# 
# Trace/spacing table is by copper weight, not layer count: 0.5oz inner 2.5mil width/3mil spacing, 1oz outer 3mil/3mil, 2oz outer 5.5mil/5.5mil. Annular ring: 3.5mil for 1oz, 4.5mil for 2oz. Min drill 0.15mm only for board thickness 1.2mm or less. PTH hole size 0.2mm or larger single side. Copper to V-cut line 0.4mm (15.748mil). Hole to hole different nets 12mil for CAF avoidance; via to via same net 8mil (0.2032mm); PTH to track 9mil (0.2286mm); NPTH to track 8mil (0.2032mm); SMD pad to track 4mil (0.1016mm); SMD pad to SMD pad 0.15mm; pad to pad with hole different nets 0.40mm. Mask sliver (solder bridge dam): green 3.5mil, black/white 5mil (0.127mm), other colors 4mil (0.1016mm). Silk line width: silkscreen printing 5mil (0.127mm), printer printing 3mil (0.0762mm). Finished copper outer 1oz/2oz, inner 0.5oz/1oz/2oz. Surface finish cell left blank on page. BGA 1oz: min pad 0.2mm, min pad distance 0.15mm. Layer count 1 to 32 supported.
# 
# Sources:
# - https://www.nextpcb.com/pcb-capabilities (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.0635mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.0762mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.15mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.3278mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.2mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.0762mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))