PCB Design Rules - kicad/macrofab-extended-2L.kicad_dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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(version 1)

# MacroFab 2-layer design rules (extended process)
# 
# Min trace width: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper
# Min spacing: 0.0762 mm (3.0 mil) - extended specs, not available on 2 oz copper
# Min drill: 0.1016 mm (4.0 mil)
# Min via: 0.1016 mm hole / 0.254 mm pad
# Annular ring: via 0.0762 mm
# Copper to board edge: 0.0762 mm
# Hole to hole: 0.1524 mm
# Board thickness options: 1.6 mm
# Copper weight options: 0.5 oz, 1 oz
# Surface finishes: ENIG
# Max board size: 378.46 x 378.46 mm
# 
# Extended DRC minimums as published. Board thickness 1.6 mm standard, other custom thicknesses supported; thickness tolerance T below 1.0 mm plus minus 15 percent, 1.0 to 1.6 mm plus minus 10 percent, T at or above 1.6 mm plus minus 10 percent. Min via pad derived from published min drill plus 2x annular ring: 4 mil plus 6 mil. NPTH hole size tolerance plus minus 0.05 mm, PTH plus minus 0.08 mm. Board edge tolerance plus minus 0.15 mm. Extended option disabled for 2 oz copper. Paste aperture min 0.1524 mm, paste clearance 0.1524 mm. Silkscreen text height min 0.8 mm.
# 
# Sources:
# - https://www.macrofab.com/capabilities/ (read 2026-09-03)
# - https://www.macrofab.com/pcba/specs/ (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.0762mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.0762mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.1016mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.254mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.0762mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.127mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))