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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago
(version 1)

# Eurocircuits 4-layer design rules (proto process)
# 
# Min trace width: 0.15 mm (5.91 mil) - outer and inner layers, pattern class 6
# Min spacing: 0.15 mm (5.91 mil) - pattern class 6; class 5 is 0.175 mm (6.8898 mil)
# Min drill: 0.25 mm (9.84 mil)
# Min via: 0.25 mm hole / 0.6 mm pad
# Annular ring: via 0.125 mm
# Copper to board edge: 0.25 mm
# Hole to hole: 0.25 mm
# Board thickness options: 1.55 mm
# Copper weight options: 0.5 oz, 1 oz
# Surface finishes: ENIG, LF HAL
# Max board size: 500 x 425 mm
# 
# 4 layer max board size 500 x 425 mm. Same build parameters as 2 layer. Blind and buried vias not available in PCB proto.
# 
# Sources:
# - https://www.eurocircuits.com/services/pcb-proto/ (read 2026-09-03)
# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.15mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.15mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.25mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.6mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.25mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.1mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))