skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
(version 1)
# Eurocircuits 6-layer design rules (standard process)
#
# Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)
# Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)
# Min drill: 0.1 mm (3.94 mil)
# Min via: 0.1 mm hole / 0.4 mm pad
# Annular ring: via 0.125 mm
# Copper to board edge: 0.25 mm
# Hole to hole: 0.25 mm
# Board thickness options: 1.55 mm
# Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz
# Surface finishes: ENIG, LF HAL, Immersion Silver
# Max board size: 500 x 425 mm
#
# 6 and 8 layers pooling in STANDARD pool; 10 to 16 layers non-pooling. Pooling board thickness for multilayers 6 layers and above is 1.55 mm. Same pattern and drill classification system applies.
#
# Sources:
# - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)
(rule "min-track-width"
(constraint track_width (min 0.1mm))
(layer "*.Cu")
(condition "A.type == 'track'"))
(rule "min-clearance"
(constraint clearance (min 0.1mm))
(condition "A.type == 'track' && B.type == 'track'"))
(rule "min-hole"
(constraint hole (min 0.1mm))
(condition "A.type == 'pad' || A.type == 'via'"))
(rule "min-via-diameter"
(constraint via_diameter (min 0.4mm))
(condition "A.type == 'via'"))
(rule "min-edge-clearance"
(constraint edge_clearance (min 0.25mm))
(condition "A.type == 'track'"))
(rule "min-silk-thickness"
(constraint text_thickness (min 0.1mm))
(layer "*.SilkS")
(condition "A.type == 'text' || A.type == 'graphic'"))