PCB Design Rules - kicad/eurocircuits-4L.kicad_dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

Overview Files Skills Discover Packages Releases Dependencies Issues1 Breadcrumbs Pull Requests1 Activity

main

History Download

John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

(version 1)

# Eurocircuits 4-layer design rules (standard process)
# 
# Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); inner layer same classification values
# Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); pattern class 6 is 0.150 mm (5.9055 mil)
# Min drill: 0.1 mm (3.94 mil)
# Min via: 0.1 mm hole / 0.4 mm pad
# Annular ring: via 0.125 mm
# Copper to board edge: 0.25 mm
# Hole to hole: 0.25 mm
# Board thickness options: 1.0 mm, 1.55 mm
# Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz
# Surface finishes: ENIG, LF HAL, Immersion Silver
# Max board size: 500 x 425 mm
# 
# 4 layer pooling board thickness 1.00 mm; 1.55 mm pooling for 6 to 16 layers. Multilayer max dimension 500 x 425 mm. Standard buildups pooled, 8 predefined non-pooling builds; blind and buried vias non-pooling specials. Base copper inner layers pooling 18 µm and 35 µm.
# 
# Sources:
# - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)
# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.1mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.1mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.1mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.4mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.25mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.1mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))