PCB Design Rules

(version 1)

# Eurocircuits 2-layer design rules (standard process)
# 
# Min trace width: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil)
# Min spacing: 0.1 mm (3.94 mil) - pooling; non-pooling 0.090 mm (3.5433 mil); pattern class table: class 6 track/gap 0.150 mm (5.9055 mil), class 7 0.125 mm (4.9213 mil), class 8 0.100 mm (3.937 mil), class 9 0.090 mm (3.5433 mil), class 5 0.175 mm (6.8898 mil)
# Min drill: 0.1 mm (3.94 mil)
# Min via: 0.1 mm hole / 0.4 mm pad
# Annular ring: via 0.125 mm
# Copper to board edge: 0.25 mm
# Hole to hole: 0.25 mm
# Board thickness options: 1.0 mm, 1.55 mm, 2.4 mm
# Copper weight options: 0.5 oz, 0.67 oz, 1 oz, 2 oz
# Surface finishes: ENIG, LF HAL, Immersion Silver
# Max board size: 580 x 425 mm
# 
# Min board 5 x 5 mm. Base copper foil pooling 2 layer: 12 µm (0.33 oz), 18 µm (0.5 oz), 35 µm (1 oz), 70 µm (2 oz); inner layers 18 µm and 35 µm. Minimum pad diameter: outer PTH finished hole plus 0.300 mm, outer NPTH plus 0.200 mm, inner PTH plus 0.350 mm, inner NPTH plus 0.250 mm. Classification min pattern values also limited by base copper foil: 12 µm 0.090 mm (3.5 mil), 18 µm 0.100 mm (4 mil), 35 µm 0.125 mm (5 mil), 70 µm 0.200 mm (8 mil), 105 µm 0.250 mm (10 mil), for both outer and inner layers. Drill class minimum TOOLSIZE: class A 0.60 mm (23.622 mil), B 0.45 mm (17.7165 mil), C 0.35 mm (13.7795 mil), D 0.25 mm (9.8425 mil), E 0.20 mm (7.874 mil); max board thickness per drill class: A and B 3.20 mm, C 2.40 mm, D 2.00 mm, E 1.60 mm; aspect ratio 1:8. TOOLSIZE equals finished PTH size plus 0.10 mm (4 mil). Soldermask colors pooling: green, blue, black, white, red; non-pooling transparent. Legend white one or both sides, non-pooling black and white.
# 
# Sources:
# - https://www.eurocircuits.com/services/standard-pool/ (read 2026-09-03)
# - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03)
# - https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.1mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.1mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.1mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.4mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.25mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.1mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))