skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
(version 1)
# Elecrow 4-layer design rules (standard process)
#
# Min trace width: 0.1524 mm (6.0 mil) - minimum, recommend greater than 8 mil
# Min spacing: 0.1524 mm (6.0 mil) - trace to trace, minimum, recommend greater than 8 mil; pad to pad minimum is 8 mil (0.2032 mm)
# Min drill: 0.3 mm (11.81 mil)
# Min via: 0.3 mm hole
# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm
# Copper weight options: 1 oz, 2 oz
# Surface finishes: HASL, HASL Lead Free, ENIG
# Max board size: 550 x 550 mm
#
# Same published spec table as 2 layer: multi layers 1-2-4-6-8 share these limits. 4 layer adds two inner layers (G1, G2 gerbers). Inner layer copper 17um (0.5 oz) or 35um (1 oz).
#
# Sources:
# - https://www.elecrow.com/pcb-manufacturing.html (read 2026-09-03)
(rule "min-track-width"
(constraint track_width (min 0.1524mm))
(layer "*.Cu")
(condition "A.type == 'track'"))
(rule "min-clearance"
(constraint clearance (min 0.1524mm))
(condition "A.type == 'track' && B.type == 'track'"))
(rule "min-hole"
(constraint hole (min 0.3mm))
(condition "A.type == 'pad' || A.type == 'via'"))
(rule "min-silk-thickness"
(constraint text_thickness (min 0.15mm))
(layer "*.SilkS")
(condition "A.type == 'text' || A.type == 'graphic'"))