skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
(version 1)
# ALLPCB 2-layer design rules (advanced process)
#
# Min trace width: 0.076 mm (3.0 mil) - 1oz copper
# Min spacing: 0.076 mm (3.0 mil) - 1oz copper
# Min drill: 0.15 mm (5.91 mil)
# Min via: 0.2 mm hole / 0.5 mm pad
# Annular ring: via 0.18 mm
# Copper to board edge: 0.3 mm
# Board thickness options: 0.4 mm, 4.0 mm
# Copper weight options: 1 oz, 2 oz, 3 oz, 4 oz, 5 oz, 6 oz
# Surface finishes: Bare Copper, OSP, HASL With Lead, HASL Lead-free, Immersion Gold, Immersion Tin, Immersion Silver, Nickel Palladium Gold, OSP plus Selective Immersion Gold, Lead-free HASL plus Selective Immersion Gold, Lead-free HASL plus Selective Gold Plating
# Max board size: 630 x 520 mm
#
# Double-side board via/pad: 0.2mm inner diameter, 0.5mm outer diameter; outer diameter must be 0.1mm larger than inner, 0.15mm preferred; preferred min via hole 0.2mm. Trace/spacing by copper weight: 1oz 0.076mm, 2oz 0.14mm (5.5118mil), 3oz 0.2mm (7.874mil), 4oz 0.25mm (9.8425mil), 5oz 0.35mm (13.7795mil), 6oz 0.45mm (17.7165mil). Trace width tolerance ±20%. Annular ring: plated DIP holes 1oz recommended 0.2mm, limit 0.18mm; non-plated DIP holes recommended 0.4mm (15.748mil). Min plated slot 0.7mm (27.5591mil), min non-plated slot 0.8mm (31.4961mil). Board thickness to min plated hole ratio 10:1. Plated half hole diameter 0.4mm or more, spacing 0.35mm (13.7795mil). Min single PCB size 10x5mm. Copper to board edge 0.3mm at non-stamp-hole panel areas; V-cut line to copper 0.4mm. Mask sliver recorded from min solder bridge width: green 0.075mm, other colors 0.125mm (4.9213mil). Silk text height 0.75mm (29.5276mil). BGA pad diameter 0.2mm or more. Edge rail 4mm or more.
#
# Sources:
# - https://www.allpcb.com/advanced_pcb_manufacturing_capability.html (read 2026-09-03)
(rule "min-track-width"
(constraint track_width (min 0.076mm))
(layer "*.Cu")
(condition "A.type == 'track'"))
(rule "min-clearance"
(constraint clearance (min 0.076mm))
(condition "A.type == 'track' && B.type == 'track'"))
(rule "min-hole"
(constraint hole (min 0.15mm))
(condition "A.type == 'pad' || A.type == 'via'"))
(rule "min-via-diameter"
(constraint via_diameter (min 0.5mm))
(condition "A.type == 'via'"))
(rule "min-edge-clearance"
(constraint edge_clearance (min 0.3mm))
(condition "A.type == 'track'"))
(rule "min-silk-thickness"
(constraint text_thickness (min 0.1mm))
(layer "*.SilkS")
(condition "A.type == 'text' || A.type == 'graphic'"))