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PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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pcb-design-rules / kicad / allpcb-2L.kicad_dru
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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago
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(version 1)

# ALLPCB 2-layer design rules (standard process)
# 
# Min trace width: 0.1 mm (3.94 mil) - all copper weights; vendor suggests 6mil (0.15mm) or more to save cost
# Min spacing: 0.1 mm (3.94 mil) - all copper weights; vendor suggests 6mil (0.15mm) or more to save cost
# Min drill: 0.2 mm (7.87 mil)
# Min via: 0.2 mm hole / 0.506 mm pad
# Annular ring: via 0.153 mm
# Copper to board edge: 0.3 mm
# Hole to hole: 0.2032 mm
# Board thickness options: 0.4 mm, 3.2 mm
# Copper weight options: 0.5 oz, 1 oz, 2 oz
# Surface finishes: HASL, Immersion Gold, Immersion Silver, Immersion Tin, OSP, Hard Gold plating, Soft Gold plating, NiPdAu
# Max board size: 506 x 580 mm
# 
# Single published limit set covers 1 to 14 layers, so this entry also applies to 4 and 6 layer boards. Board thickness is a continuous 0.4 to 3.2mm range. Copper: outer 1oz to 2oz (35 to 70um), inner 0.5oz to 2oz (18 to 70um). Min dimension 80x80mm. Drill range 0.2 to 6.5mm, finished CNC hole 0.2 to 6.5mm, hole size tolerance ±0.075mm. Copper to V-cut line 0.4mm (15.748mil) for panelized boards. Via space same net 8mil (0.2032mm), different nets 17mil (0.4318mm), component vias different nets 24mil (0.6096mm). Annular ring 6mil or larger where surrounded by traces. Min slot width 0.6mm, finished slot 0.45mm for HASL and 0.5mm for other finishes. Board thickness to via diameter ratio 6:1, 7:1 to 8:1 adds a fabrication day. Min character height 0.8mm (31.4961mil), width to height ratio 1:5. Mask sliver recorded from solder mask bridge value 0.1mm (price may rise).
# 
# Sources:
# - https://www.allpcb.com/standard_pcb_manufacturing_capability.html (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.1mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.1mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.2mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.506mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.3mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.15mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))